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![Michael Niedermayer](/assets/img/avatar_default.png)
* commit 'e74433a8e6fc00c8dbde293c97a3e45384c2c1d9': dsputil: Split clear_block*/fill_block* off into a separate context Conflicts: configure libavcodec/asvdec.c libavcodec/dnxhddec.c libavcodec/dnxhdenc.c libavcodec/dsputil.h libavcodec/eamad.c libavcodec/intrax8.c libavcodec/mjpegdec.c libavcodec/ppc/dsputil_ppc.c libavcodec/vc1dec.c libavcodec/x86/dsputil_init.c libavcodec/x86/dsputil_mmx.c Merged-by: Michael Niedermayer <michaelni@gmx.at>
170 lines
5.4 KiB
C
170 lines
5.4 KiB
C
/*
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* Copyright (c) 2002 Brian Foley
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* Copyright (c) 2002 Dieter Shirley
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* Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#if HAVE_ALTIVEC_H
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#include <altivec.h>
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#endif
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#include <string.h>
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#include "libavutil/attributes.h"
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#include "libavutil/cpu.h"
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#include "libavutil/mem.h"
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#include "libavutil/ppc/cpu.h"
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#include "libavutil/ppc/types_altivec.h"
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#include "libavcodec/blockdsp.h"
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/* ***** WARNING ***** WARNING ***** WARNING ***** */
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/*
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* clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with
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* a cache line size not equal to 32 bytes. Fortunately all processors used
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* by Apple up to at least the 7450 (AKA second generation G4) use 32-byte
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* cache lines. This is due to the use of the 'dcbz' instruction. It simply
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* clears a single cache line to zero, so you need to know the cache line
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* size to use it! It's absurd, but it's fast...
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*
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* update 24/06/2003: Apple released the G5 yesterday, with a PPC970.
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* cache line size: 128 bytes. Oups.
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* The semantics of dcbz was changed, it always clears 32 bytes. So the function
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* below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
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* which is defined to clear a cache line (as dcbz before). So we can still
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* distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
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*
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* see <http://developer.apple.com/technotes/tn/tn2087.html>
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* and <http://developer.apple.com/technotes/tn/tn2086.html>
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*/
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static void clear_blocks_dcbz32_ppc(int16_t *blocks)
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{
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register int misal = (unsigned long) blocks & 0x00000010, i = 0;
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if (misal) {
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((unsigned long *) blocks)[0] = 0L;
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((unsigned long *) blocks)[1] = 0L;
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((unsigned long *) blocks)[2] = 0L;
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((unsigned long *) blocks)[3] = 0L;
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i += 16;
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}
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for (; i < sizeof(int16_t) * 6 * 64 - 31; i += 32)
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__asm__ volatile ("dcbz %0,%1" :: "b" (blocks), "r" (i) : "memory");
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if (misal) {
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((unsigned long *) blocks)[188] = 0L;
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((unsigned long *) blocks)[189] = 0L;
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((unsigned long *) blocks)[190] = 0L;
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((unsigned long *) blocks)[191] = 0L;
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i += 16;
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}
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}
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/* Same as above, when dcbzl clears a whole 128 bytes cache line
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* i.e. the PPC970 AKA G5. */
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static void clear_blocks_dcbz128_ppc(int16_t *blocks)
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{
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#if HAVE_DCBZL
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register int misal = (unsigned long) blocks & 0x0000007f, i = 0;
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if (misal) {
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/* We could probably also optimize this case,
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* but there's not much point as the machines
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* aren't available yet (2003-06-26). */
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memset(blocks, 0, sizeof(int16_t) * 6 * 64);
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} else {
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for (; i < sizeof(int16_t) * 6 * 64; i += 128)
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__asm__ volatile ("dcbzl %0,%1" :: "b" (blocks), "r" (i) : "memory");
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}
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#else
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memset(blocks, 0, sizeof(int16_t) * 6 * 64);
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#endif
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}
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/* Check dcbz report how many bytes are set to 0 by dcbz. */
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/* update 24/06/2003: Replace dcbz by dcbzl to get the intended effect
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* (Apple "fixed" dcbz). Unfortunately this cannot be used unless the
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* assembler knows about dcbzl ... */
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static long check_dcbzl_effect(void)
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{
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long count = 0;
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#if HAVE_DCBZL
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register char *fakedata = av_malloc(1024);
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register char *fakedata_middle;
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register long zero = 0, i = 0;
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if (!fakedata)
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return 0L;
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fakedata_middle = fakedata + 512;
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memset(fakedata, 0xFF, 1024);
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/* Below the constraint "b" seems to mean "address base register"
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* in gcc-3.3 / RS/6000 speaks. Seems to avoid using r0, so.... */
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__asm__ volatile ("dcbzl %0, %1" :: "b" (fakedata_middle), "r" (zero));
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for (i = 0; i < 1024; i++)
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if (fakedata[i] == (char) 0)
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count++;
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av_free(fakedata);
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#endif
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return count;
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}
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#if HAVE_ALTIVEC
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static void clear_block_altivec(int16_t *block)
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{
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LOAD_ZERO;
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vec_st(zero_s16v, 0, block);
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vec_st(zero_s16v, 16, block);
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vec_st(zero_s16v, 32, block);
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vec_st(zero_s16v, 48, block);
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vec_st(zero_s16v, 64, block);
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vec_st(zero_s16v, 80, block);
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vec_st(zero_s16v, 96, block);
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vec_st(zero_s16v, 112, block);
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}
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#endif /* HAVE_ALTIVEC */
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av_cold void ff_blockdsp_init_ppc(BlockDSPContext *c, unsigned high_bit_depth)
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{
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// common optimizations whether AltiVec is available or not
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if (!high_bit_depth) {
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switch (check_dcbzl_effect()) {
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case 32:
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c->clear_blocks = clear_blocks_dcbz32_ppc;
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break;
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case 128:
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c->clear_blocks = clear_blocks_dcbz128_ppc;
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break;
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default:
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break;
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}
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}
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#if HAVE_ALTIVEC
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if (!PPC_ALTIVEC(av_get_cpu_flags()))
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return;
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if (!high_bit_depth)
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c->clear_block = clear_block_altivec;
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#endif /* HAVE_ALTIVEC */
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}
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