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![James Almer](/assets/img/avatar_default.png)
~20% faster than ssse3. Also enabled for x86_32 Reviewed-by: Ronald S. Bultje <rsbultje@gmail.com> Signed-off-by: James Almer <jamrial@gmail.com>
248 lines
9.2 KiB
NASM
248 lines
9.2 KiB
NASM
;*****************************************************************************
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;* x86-optimized functions for ssim filter
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;*
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;* Copyright (C) 2015 Ronald S. Bultje <rsbultje@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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pw_1: times 8 dw 1
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ssim_c1: times 4 dd 416 ;(.01*.01*255*255*64 + .5)
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ssim_c2: times 4 dd 235963 ;(.03*.03*255*255*64*63 + .5)
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SECTION .text
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%macro SSIM_4X4_LINE 1
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%if ARCH_X86_64
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cglobal ssim_4x4_line, 6, 8, %1, buf, buf_stride, ref, ref_stride, sums, w, buf_stride3, ref_stride3
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%else
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cglobal ssim_4x4_line, 5, 7, %1, buf, buf_stride, ref, ref_stride, sums, buf_stride3, ref_stride3
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%define wd r5mp
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%endif
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lea ref_stride3q, [ref_strideq*3]
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lea buf_stride3q, [buf_strideq*3]
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%if notcpuflag(xop)
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pxor m7, m7
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mova m15, [pw_1]
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%endif
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.loop:
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%if cpuflag(xop)
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pmovzxbw m0, [bufq+buf_strideq*0]
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pmovzxbw m1, [refq+ref_strideq*0]
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pmaddwd m4, m0, m0
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pmaddwd m6, m0, m1
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pmovzxbw m2, [bufq+buf_strideq*1]
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vpmadcswd m4, m1, m1, m4
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pmovzxbw m3, [refq+ref_strideq*1]
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paddw m0, m2
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vpmadcswd m4, m2, m2, m4
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vpmadcswd m6, m2, m3, m6
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paddw m1, m3
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vpmadcswd m4, m3, m3, m4
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pmovzxbw m2, [bufq+buf_strideq*2]
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pmovzxbw m3, [refq+ref_strideq*2]
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vpmadcswd m4, m2, m2, m4
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vpmadcswd m6, m2, m3, m6
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pmovzxbw m5, [bufq+buf_stride3q]
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pmovzxbw m7, [refq+ref_stride3q]
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vpmadcswd m4, m3, m3, m4
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vpmadcswd m6, m5, m7, m6
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paddw m0, m2
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paddw m1, m3
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vpmadcswd m4, m5, m5, m4
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paddw m0, m5
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paddw m1, m7
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vpmadcswd m4, m7, m7, m4
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%else
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movh m0, [bufq+buf_strideq*0] ; a1
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movh m1, [refq+ref_strideq*0] ; b1
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movh m2, [bufq+buf_strideq*1] ; a2
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movh m3, [refq+ref_strideq*1] ; b2
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punpcklbw m0, m7 ; s1 [word]
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punpcklbw m1, m7 ; s2 [word]
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punpcklbw m2, m7 ; s1 [word]
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punpcklbw m3, m7 ; s2 [word]
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pmaddwd m4, m0, m0 ; a1 * a1
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pmaddwd m5, m1, m1 ; b1 * b1
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pmaddwd m8, m2, m2 ; a2 * a2
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pmaddwd m9, m3, m3 ; b2 * b2
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paddd m4, m5 ; ss
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paddd m8, m9 ; ss
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pmaddwd m6, m0, m1 ; a1 * b1 = ss12
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pmaddwd m5, m2, m3 ; a2 * b2 = ss12
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paddw m0, m2
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paddw m1, m3
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paddd m6, m5 ; s12
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paddd m4, m8 ; ss
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movh m2, [bufq+buf_strideq*2] ; a3
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movh m3, [refq+ref_strideq*2] ; b3
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movh m5, [bufq+buf_stride3q] ; a4
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movh m8, [refq+ref_stride3q] ; b4
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punpcklbw m2, m7 ; s1 [word]
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punpcklbw m3, m7 ; s2 [word]
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punpcklbw m5, m7 ; s1 [word]
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punpcklbw m8, m7 ; s2 [word]
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pmaddwd m9, m2, m2 ; a3 * a3
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pmaddwd m10, m3, m3 ; b3 * b3
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pmaddwd m12, m5, m5 ; a4 * a4
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pmaddwd m13, m8, m8 ; b4 * b4
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pmaddwd m11, m2, m3 ; a3 * b3 = ss12
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pmaddwd m14, m5, m8 ; a4 * b4 = ss12
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paddd m9, m10
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paddd m12, m13
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paddw m0, m2
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paddw m1, m3
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paddw m0, m5
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paddw m1, m8
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paddd m6, m11
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paddd m4, m9
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paddd m6, m14
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paddd m4, m12
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%endif
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; m0 = [word] s1 a,a,a,a,b,b,b,b
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; m1 = [word] s2 a,a,a,a,b,b,b,b
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; m4 = [dword] ss a,a,b,b
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; m6 = [dword] s12 a,a,b,b
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%if cpuflag(xop)
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vphaddwq m0, m0 ; [dword] s1 a, 0, b, 0
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vphaddwq m1, m1 ; [dword] s2 a, 0, b, 0
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vphadddq m4, m4 ; [dword] ss a, 0, b, 0
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vphadddq m6, m6 ; [dword] s12 a, 0, b, 0
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punpckhdq m2, m0, m1 ; [dword] s1 b, s2 b, 0, 0
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punpckldq m0, m1 ; [dword] s1 a, s2 a, 0, 0
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punpckhdq m3, m4, m6 ; [dword] ss b, s12 b, 0, 0
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punpckldq m4, m6 ; [dword] ss a, s12 a, 0, 0
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punpcklqdq m1, m2, m3 ; [dword] b s1, s2, ss, s12
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punpcklqdq m0, m4 ; [dword] a s1, s2, ss, s12
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%else
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pmaddwd m0, m15 ; [dword] s1 a,a,b,b
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pmaddwd m1, m15 ; [dword] s2 a,a,b,b
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phaddd m0, m4 ; [dword] s1 a, b, ss a, b
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phaddd m1, m6 ; [dword] s2 a, b, s12 a, b
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punpckhdq m2, m0, m1 ; [dword] ss a, s12 a, ss b, s12 b
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punpckldq m0, m1 ; [dword] s1 a, s2 a, s1 b, s2 b
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punpckhqdq m1, m0, m2 ; [dword] b s1, s2, ss, s12
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punpcklqdq m0, m2 ; [dword] a s1, s2, ss, s12
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%endif
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mova [sumsq+ 0], m0
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mova [sumsq+mmsize], m1
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add bufq, mmsize/2
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add refq, mmsize/2
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add sumsq, mmsize*2
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sub wd, mmsize/8
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jg .loop
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RET
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%endmacro
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%if ARCH_X86_64
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INIT_XMM ssse3
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SSIM_4X4_LINE 16
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%endif
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%if HAVE_XOP_EXTERNAL
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INIT_XMM xop
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SSIM_4X4_LINE 8
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%endif
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INIT_XMM sse4
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cglobal ssim_end_line, 3, 3, 6, sum0, sum1, w
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pxor m0, m0
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.loop:
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mova m1, [sum0q+mmsize*0]
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mova m2, [sum0q+mmsize*1]
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mova m3, [sum0q+mmsize*2]
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mova m4, [sum0q+mmsize*3]
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paddd m1, [sum1q+mmsize*0]
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paddd m2, [sum1q+mmsize*1]
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paddd m3, [sum1q+mmsize*2]
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paddd m4, [sum1q+mmsize*3]
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paddd m1, m2
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paddd m2, m3
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paddd m3, m4
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paddd m4, [sum0q+mmsize*4]
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paddd m4, [sum1q+mmsize*4]
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TRANSPOSE4x4D 1, 2, 3, 4, 5
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; m1 = fs1, m2 = fs2, m3 = fss, m4 = fs12
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pslld m3, 6
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pslld m4, 6
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pmulld m5, m1, m2 ; fs1 * fs2
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pmulld m1, m1 ; fs1 * fs1
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pmulld m2, m2 ; fs2 * fs2
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psubd m3, m1
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psubd m4, m5 ; covariance
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psubd m3, m2 ; variance
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; m1 = fs1 * fs1, m2 = fs2 * fs2, m3 = variance, m4 = covariance, m5 = fs1 * fs2
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paddd m4, m4 ; 2 * covariance
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paddd m5, m5 ; 2 * fs1 * fs2
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paddd m1, m2 ; fs1 * fs1 + fs2 * fs2
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paddd m3, [ssim_c2] ; variance + ssim_c2
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paddd m4, [ssim_c2] ; 2 * covariance + ssim_c2
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paddd m5, [ssim_c1] ; 2 * fs1 * fs2 + ssim_c1
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paddd m1, [ssim_c1] ; fs1 * fs1 + fs2 * fs2 + ssim_c1
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; convert to float
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cvtdq2ps m3, m3
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cvtdq2ps m4, m4
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cvtdq2ps m5, m5
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cvtdq2ps m1, m1
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mulps m4, m5
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mulps m3, m1
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divps m4, m3 ; ssim_endl
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addps m0, m4 ; ssim
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add sum0q, mmsize*4
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add sum1q, mmsize*4
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sub wd, 4
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jg .loop
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; subps the ones we added too much
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test wd, wd
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jz .end
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add wd, 4
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test wd, 2
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jz .skip2
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psrldq m4, 8
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.skip2:
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test wd, 1
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jz .skip1
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psrldq m4, 4
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.skip1:
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subps m0, m4
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.end:
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movhlps m4, m0
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addps m0, m4
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movss m4, m0
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shufps m0, m0, 1
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addss m0, m4
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%if ARCH_X86_32
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movss r0m, m0
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fld r0mp
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%endif
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RET
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