mirror of
https://git.videolan.org/git/ffmpeg.git
synced 2024-09-05 15:58:07 +02:00
407 lines
9.8 KiB
NASM
407 lines
9.8 KiB
NASM
;******************************************************************************
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;* SIMD lossless video DSP utils
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;* Copyright (c) 2008 Loren Merritt
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;* Copyright (c) 2014 Michael Niedermayer
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;* Copyright (c) 2017 Jokyo Images
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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cextern pb_15
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pb_zzzzzzzz77777777: times 8 db -1
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pb_7: times 8 db 7
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pb_ef: times 8 db 14,15
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pb_67: times 8 db 6, 7
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pb_zzzz3333zzzzbbbb: db -1,-1,-1,-1,3,3,3,3,-1,-1,-1,-1,11,11,11,11
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pb_zz11zz55zz99zzdd: db -1,-1,1,1,-1,-1,5,5,-1,-1,9,9,-1,-1,13,13
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pb_zzzz2323zzzzabab: db -1,-1,-1,-1, 2, 3, 2, 3,-1,-1,-1,-1,10,11,10,11
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pb_zzzzzzzz67676767: db -1,-1,-1,-1,-1,-1,-1,-1, 6, 7, 6, 7, 6, 7, 6, 7
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SECTION .text
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;------------------------------------------------------------------------------
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; void ff_add_median_pred_mmxext(uint8_t *dst, const uint8_t *top,
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; const uint8_t *diff, int w,
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; int *left, int *left_top)
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;------------------------------------------------------------------------------
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%macro MEDIAN_PRED 0
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cglobal add_median_pred, 6,6,8, dst, top, diff, w, left, left_top
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movu m0, [topq]
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mova m2, m0
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movd m4, [left_topq]
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LSHIFT m2, 1
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mova m1, m0
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por m4, m2
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movd m3, [leftq]
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psubb m0, m4 ; t-tl
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add dstq, wq
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add topq, wq
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add diffq, wq
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neg wq
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jmp .skip
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.loop:
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movu m4, [topq+wq]
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mova m0, m4
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LSHIFT m4, 1
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por m4, m1
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mova m1, m0 ; t
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psubb m0, m4 ; t-tl
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.skip:
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movu m2, [diffq+wq]
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%assign i 0
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%rep mmsize
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mova m4, m0
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paddb m4, m3 ; t-tl+l
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mova m5, m3
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pmaxub m3, m1
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pminub m5, m1
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pminub m3, m4
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pmaxub m3, m5 ; median
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paddb m3, m2 ; +residual
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%if i==0
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mova m7, m3
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LSHIFT m7, mmsize-1
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%else
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mova m6, m3
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RSHIFT m7, 1
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LSHIFT m6, mmsize-1
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por m7, m6
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%endif
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%if i<mmsize-1
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RSHIFT m0, 1
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RSHIFT m1, 1
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RSHIFT m2, 1
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%endif
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%assign i i+1
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%endrep
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movu [dstq+wq], m7
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add wq, mmsize
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jl .loop
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movzx r2d, byte [dstq-1]
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mov [leftq], r2d
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movzx r2d, byte [topq-1]
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mov [left_topq], r2d
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RET
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%endmacro
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%if ARCH_X86_32
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INIT_MMX mmxext
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MEDIAN_PRED
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%endif
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INIT_XMM sse2
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MEDIAN_PRED
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%macro ADD_LEFT_LOOP 2 ; %1 = dst_is_aligned, %2 = src_is_aligned
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add srcq, wq
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add dstq, wq
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neg wq
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%%.loop:
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pshufb xm0, xm5
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%if %2
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mova m1, [srcq+wq]
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%else
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movu m1, [srcq+wq]
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%endif
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psllw m2, m1, 8
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paddb m1, m2
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pshufb m2, m1, m3
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paddb m1, m2
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pshufb m2, m1, m4
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paddb m1, m2
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%if mmsize >= 16
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pshufb m2, m1, m6
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paddb m1, m2
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%endif
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paddb xm0, xm1
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%if %1
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mova [dstq+wq], xm0
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%else
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movq [dstq+wq], xm0
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movhps [dstq+wq+8], xm0
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%endif
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%if mmsize == 32
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vextracti128 xm2, m1, 1 ; get second lane of the ymm
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pshufb xm0, xm5 ; set alls val to last val of the first lane
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paddb xm0, xm2
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;store val
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%if %1
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mova [dstq+wq+16], xm0
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%else;
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movq [dstq+wq+16], xm0
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movhps [dstq+wq+16+8], xm0
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%endif
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%endif
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add wq, mmsize
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jl %%.loop
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%if mmsize == 32
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movzx eax, byte [dstq - 1]
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%else;
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mov eax, mmsize-1
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sub eax, wd
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movd m1, eax
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pshufb m0, m1
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movd eax, m0
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%endif
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RET
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%endmacro
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;------------------------------------------------------------------------------
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; int ff_add_left_pred(uint8_t *dst, const uint8_t *src, int w, int left)
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;------------------------------------------------------------------------------
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INIT_MMX ssse3
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cglobal add_left_pred, 3,3,7, dst, src, w, left
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.skip_prologue:
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mova m5, [pb_7]
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mova m4, [pb_zzzz3333zzzzbbbb]
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mova m3, [pb_zz11zz55zz99zzdd]
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movd m0, leftm
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psllq m0, 56
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ADD_LEFT_LOOP 1, 1
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%macro ADD_LEFT_PRED_UNALIGNED 0
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cglobal add_left_pred_unaligned, 3,3,7, dst, src, w, left
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mova xm5, [pb_15]
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VBROADCASTI128 m6, [pb_zzzzzzzz77777777]
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VBROADCASTI128 m4, [pb_zzzz3333zzzzbbbb]
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VBROADCASTI128 m3, [pb_zz11zz55zz99zzdd]
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movd xm0, leftm
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pslldq xm0, 15
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test srcq, mmsize - 1
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jnz .src_unaligned
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test dstq, mmsize - 1
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jnz .dst_unaligned
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ADD_LEFT_LOOP 1, 1
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.dst_unaligned:
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ADD_LEFT_LOOP 0, 1
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.src_unaligned:
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ADD_LEFT_LOOP 0, 0
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%endmacro
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INIT_XMM ssse3
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ADD_LEFT_PRED_UNALIGNED
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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ADD_LEFT_PRED_UNALIGNED
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%endif
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;------------------------------------------------------------------------------
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; void ff_add_bytes(uint8_t *dst, uint8_t *src, ptrdiff_t w);
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;------------------------------------------------------------------------------
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%macro ADD_BYTES 0
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cglobal add_bytes, 3,4,2, dst, src, w, size
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mov sizeq, wq
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and sizeq, -2*mmsize
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jz .2
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add dstq, sizeq
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add srcq, sizeq
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neg sizeq
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.1:
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mova m0, [srcq + sizeq]
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mova m1, [srcq + sizeq + mmsize]
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paddb m0, [dstq + sizeq]
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paddb m1, [dstq + sizeq + mmsize]
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mova [dstq + sizeq], m0
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mova [dstq + sizeq + mmsize], m1
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add sizeq, 2*mmsize
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jl .1
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.2:
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and wq, 2*mmsize-1
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jz .end
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add dstq, wq
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add srcq, wq
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neg wq
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.3:
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mov sizeb, [srcq + wq]
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add [dstq + wq], sizeb
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inc wq
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jl .3
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.end:
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REP_RET
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%endmacro
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%if ARCH_X86_32
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INIT_MMX mmx
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ADD_BYTES
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%endif
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INIT_XMM sse2
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ADD_BYTES
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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ADD_BYTES
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%endif
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%macro ADD_HFYU_LEFT_LOOP_INT16 2 ; %1 = dst alignment (a/u), %2 = src alignment (a/u)
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add wd, wd
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add srcq, wq
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add dstq, wq
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neg wq
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%%.loop:
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mov%2 m1, [srcq+wq]
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mova m2, m1
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pslld m1, 16
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paddw m1, m2
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mova m2, m1
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pshufb m1, m3
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paddw m1, m2
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pshufb m0, m5
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%if mmsize == 16
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mova m2, m1
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pshufb m1, m4
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paddw m1, m2
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%endif
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paddw m0, m1
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pand m0, m7
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%ifidn %1, a
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mova [dstq+wq], m0
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%else
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movq [dstq+wq], m0
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movhps [dstq+wq+8], m0
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%endif
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add wq, mmsize
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jl %%.loop
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mov eax, mmsize-1
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sub eax, wd
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mov wd, eax
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shl wd, 8
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lea eax, [wd+eax-1]
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movd m1, eax
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pshufb m0, m1
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movd eax, m0
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RET
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%endmacro
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;---------------------------------------------------------------------------------------------
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; int add_left_pred_int16(uint16_t *dst, const uint16_t *src, unsigned mask, int w, int left)
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;---------------------------------------------------------------------------------------------
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INIT_MMX ssse3
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cglobal add_left_pred_int16, 4,4,8, dst, src, mask, w, left
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.skip_prologue:
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mova m5, [pb_67]
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mova m3, [pb_zzzz2323zzzzabab]
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movd m0, leftm
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psllq m0, 48
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movd m7, maskm
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SPLATW m7 ,m7
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ADD_HFYU_LEFT_LOOP_INT16 a, a
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INIT_XMM ssse3
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cglobal add_left_pred_int16_unaligned, 4,4,8, dst, src, mask, w, left
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mova m5, [pb_ef]
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mova m4, [pb_zzzzzzzz67676767]
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mova m3, [pb_zzzz2323zzzzabab]
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movd m0, leftm
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pslldq m0, 14
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movd m7, maskm
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SPLATW m7 ,m7
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test srcq, 15
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jnz .src_unaligned
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test dstq, 15
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jnz .dst_unaligned
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ADD_HFYU_LEFT_LOOP_INT16 a, a
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.dst_unaligned:
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ADD_HFYU_LEFT_LOOP_INT16 u, a
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.src_unaligned:
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ADD_HFYU_LEFT_LOOP_INT16 u, u
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;---------------------------------------------------------------------------------------------
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; void add_gradient_pred(uint8_t *src, const ptrdiff_t stride, const ptrdiff_t width)
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;---------------------------------------------------------------------------------------------
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%macro ADD_GRADIENT_PRED 0
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cglobal add_gradient_pred, 3,4,5, src, stride, width, tmp
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mova xm0, [pb_15]
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;load src - 1 in xm1
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movd xm1, [srcq-1]
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%if cpuflag(avx2)
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vpbroadcastb xm1, xm1
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%else
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pxor xm2, xm2
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pshufb xm1, xm2
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%endif
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add srcq, widthq
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neg widthq
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neg strideq
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.loop:
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lea tmpq, [srcq + strideq]
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mova m2, [tmpq + widthq] ; A = src[x-stride]
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movu m3, [tmpq + widthq - 1] ; B = src[x - (stride + 1)]
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mova m4, [srcq + widthq] ; current val (src[x])
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psubb m2, m3; A - B
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; prefix sum A-B
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pslldq m3, m2, 1
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paddb m2, m3
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pslldq m3, m2, 2
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paddb m2, m3
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pslldq m3, m2, 4
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paddb m2, m3
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pslldq m3, m2, 8
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paddb m2, m3
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; prefix sum current val
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pslldq m3, m4, 1
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paddb m4, m3
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pslldq m3, m4, 2
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paddb m4, m3
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pslldq m3, m4, 4
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paddb m4, m3
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pslldq m3, m4, 8
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paddb m4, m3
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; last sum
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paddb m2, m4 ; current + (A - B)
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paddb xm1, xm2 ; += C
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mova [srcq + widthq], xm1 ; store
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pshufb xm1, xm0 ; put last val in all val of xm1
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%if mmsize == 32
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vextracti128 xm2, m2, 1 ; get second lane of the ymm
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paddb xm1, xm2; += C
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mova [srcq + widthq + 16], xm1 ; store
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pshufb xm1, xm0 ; put last val in all val of m1
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%endif
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add widthq, mmsize
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jl .loop
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RET
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%endmacro
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INIT_XMM ssse3
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ADD_GRADIENT_PRED
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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ADD_GRADIENT_PRED
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%endif
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