1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
Fixes potential parsing failure when total number of channels indicated
by EXSS asset descriptor decreases mid-stream and stale embedded downmix
flags are referenced.
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
3. ff_pred16x16_plane_ functions only support N64 ABI now
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
1.the codes are compatible with O32 ABI
2.use uld and mtc1 to workaround cpu 3A2000 gslwlc1 bug (gslwlc1 instruction extension bug in O32 ABI)
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
3. use uld and mtc1 to workaround cpu 3A2000 gslwlc1 bug (gslwlc1 instruction extension bug in O32 ABI)
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
Values for unsupported frequencies > 48000 Hz are still included (parser
will make use of them).
Also convert sampling frequencies array to unsigned.
Signed-off-by: James Almer <jamrial@gmail.com>
Move this from separate structure field to a packet flag.
Behavior should be equivalent, except that residual flag is now properly
cleared when packet has no core frame at all.
Also print a message when forcing recovery mode due to invalid residual
to make debugging easier.
Signed-off-by: James Almer <jamrial@gmail.com>
Parse core frame size directly when searching for frame end instead of
using value extracted from previous frame.
Account for unused bits when calculating sync word distance for 14-bit
streams to avoid alias sync detection.
Parse EXSS frame size and skip over EXSS frame to avoid alias sync
detection.
Signed-off-by: James Almer <jamrial@gmail.com>
* commit '71d3305c2711d4f6ec8b92db09ff64cf4e19a58e':
h264_parse: make sure the ref count is zeroed on all failure paths
Merged-by: Derek Buitenhuis <derek.buitenhuis@gmail.com>
* commit 'a6e27f7add2698fdd89911632b570c3d0c3f2aaa':
h264: factor out parsing the reference count into a separate file
Merged-by: Derek Buitenhuis <derek.buitenhuis@gmail.com>
* commit '8d0cc8ca97678f4ca87948ebabcbaab5a4f4c1f6':
h264_parser: switch to h2645_parse for NAL unescaping
Merged-by: Hendrik Leppkes <h.leppkes@gmail.com>
Some streams contain an additional AnnexB NAL inside the mp4/nalff NALU.
This commonly occurs in interlaced streams where both fields are packed
into the same MP4 NAL with an AnnexB startcode in between.
Port handling of this format from the previous h264 nal handling.
Fixes trac #5529
1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
3. optimize some unaligned loads and stores
4. use uld and mtc1 to workaround cpu 3A2000 gslwlc1 bug (gslwlc1 instruction extension bug in O32 ABI)
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
