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lavu: add/use flag for RISC-V Zba extension 

The code was blindly assuming that Zbb or V implied Zba. While the
earlier is practically always true, the later broke some QEMU setups,
as V was introduced earlier than Zba.
This commit is contained in:
Rémi Denis-Courmont 2023-07-16 15:08:08 +03:00
parent 98e4dd39c5
commit b6585eb04c
14 changed files with 53 additions and 37 deletions
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11
libavcodec/riscv/aacpsdsp_init.c
View File

@ -43,13 +43,16 @@ av_cold void ff_psdsp_init_riscv(PSDSPContext *c)
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVV_F32) {
c->add_squares = ff_ps_add_squares_rvv;
c->mul_pair_single = ff_ps_mul_pair_single_rvv;
c->hybrid_analysis = ff_ps_hybrid_analysis_rvv;
c->stereo_interpolate[0] = ff_ps_stereo_interpolate_rvv;
if (flags & AV_CPU_FLAG_RVB_ADDR) {
c->add_squares = ff_ps_add_squares_rvv;
c->mul_pair_single = ff_ps_mul_pair_single_rvv;
c->stereo_interpolate[0] = ff_ps_stereo_interpolate_rvv;
}
}
if (flags & AV_CPU_FLAG_RVV_I32) {
if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
c->hybrid_analysis_ileave = ff_ps_hybrid_analysis_ileave_rvv;
c->hybrid_synthesis_deint = ff_ps_hybrid_synthesis_deint_rvv;
}

2
libavcodec/riscv/alacdsp_init.c
View File

@ -41,7 +41,7 @@ av_cold void ff_alacdsp_init_riscv(ALACDSPContext *c)
#if HAVE_RVV && (__riscv_xlen == 64)
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVV_I32) {
if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
c->decorrelate_stereo = ff_alac_decorrelate_stereo_rvv;
c->append_extra_bits[0] = ff_alac_append_extra_bits_mono_rvv;
c->append_extra_bits[1] = ff_alac_append_extra_bits_stereo_rvv;

12
libavcodec/riscv/audiodsp_init.c
View File

@ -38,11 +38,13 @@ av_cold void ff_audiodsp_init_riscv(AudioDSPContext *c)
if (flags & AV_CPU_FLAG_RVF)
c->vector_clipf = ff_vector_clipf_rvf;
#if HAVE_RVV
if (flags & AV_CPU_FLAG_RVV_I32) {
c->scalarproduct_int16 = ff_scalarproduct_int16_rvv;
c->vector_clip_int32 = ff_vector_clip_int32_rvv;
if (flags & AV_CPU_FLAG_RVB_ADDR) {
if (flags & AV_CPU_FLAG_RVV_I32) {
c->scalarproduct_int16 = ff_scalarproduct_int16_rvv;
c->vector_clip_int32 = ff_vector_clip_int32_rvv;
}
if (flags & AV_CPU_FLAG_RVV_F32)
c->vector_clipf = ff_vector_clipf_rvv;
}
if (flags & AV_CPU_FLAG_RVV_F32)
c->vector_clipf = ff_vector_clipf_rvv;
#endif
}

16
libavcodec/riscv/bswapdsp_init.c
View File

@ -31,16 +31,18 @@ void ff_bswap16_buf_rvv(uint16_t *dst, const uint16_t *src, int len);
av_cold void ff_bswapdsp_init_riscv(BswapDSPContext *c)
{
int cpu_flags = av_get_cpu_flags();
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVB_ADDR) {
#if (__riscv_xlen >= 64)
if (cpu_flags & AV_CPU_FLAG_RVB_BASIC)
c->bswap_buf = ff_bswap32_buf_rvb;
if (flags & AV_CPU_FLAG_RVB_BASIC)
c->bswap_buf = ff_bswap32_buf_rvb;
#endif
#if HAVE_RVV
if (cpu_flags & AV_CPU_FLAG_RVV_I32) {
c->bswap_buf = ff_bswap32_buf_rvv;
c->bswap16_buf = ff_bswap16_buf_rvv;
}
if (flags & AV_CPU_FLAG_RVV_I32) {
c->bswap_buf = ff_bswap32_buf_rvv;
c->bswap16_buf = ff_bswap16_buf_rvv;
}
#endif
}
}

2
libavcodec/riscv/fmtconvert_init.c
View File

@ -36,7 +36,7 @@ av_cold void ff_fmt_convert_init_riscv(FmtConvertContext *c)
#if HAVE_RVV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVV_F32) {
if ((flags & AV_CPU_FLAG_RVV_F32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
c->int32_to_float_fmul_scalar = ff_int32_to_float_fmul_scalar_rvv;
c->int32_to_float_fmul_array8 = ff_int32_to_float_fmul_array8_rvv;
}

3
libavcodec/riscv/h264_chroma_init_riscv.c
View File

@ -33,7 +33,8 @@ av_cold void ff_h264chroma_init_riscv(H264ChromaContext *c, int bit_depth)
#if HAVE_RVV
int flags = av_get_cpu_flags();
if (bit_depth == 8 && (flags & AV_CPU_FLAG_RVV_I32) && ff_get_rv_vlenb() >= 16) {
if (bit_depth == 8 && (flags & AV_CPU_FLAG_RVV_I32) &&
(flags & AV_CPU_FLAG_RVB_ADDR) && ff_get_rv_vlenb() >= 16) {
c->put_h264_chroma_pixels_tab[0] = h264_put_chroma_mc8_rvv;
c->avg_h264_chroma_pixels_tab[0] = h264_avg_chroma_mc8_rvv;
}

2
libavcodec/riscv/vorbisdsp_init.c
View File

@ -31,7 +31,7 @@ av_cold void ff_vorbisdsp_init_riscv(VorbisDSPContext *c)
#if HAVE_RVV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVV_I32)
if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR))
c->vorbis_inverse_coupling = ff_vorbis_inverse_coupling_rvv;
#endif
}

1
libavutil/cpu.c
View File

@ -190,6 +190,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
{ "rvv-f32", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 }, .unit = "flags" },
{ "rvv-i64", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 }, .unit = "flags" },
{ "rvv", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 }, .unit = "flags" },
{ "rvb-addr",NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_ADDR }, .unit = "flags" },
{ "rvb-basic",NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC }, .unit = "flags" },
#endif
{ NULL },

1
libavutil/cpu.h
View File

@ -89,6 +89,7 @@
#define AV_CPU_FLAG_RVV_I64 (1 << 5) ///< Vectors of 64-bit int's */
#define AV_CPU_FLAG_RVV_F64 (1 << 6) ///< Vectors of double's
#define AV_CPU_FLAG_RVB_BASIC (1 << 7) ///< Basic bit-manipulations
#define AV_CPU_FLAG_RVB_ADDR (1 << 8) ///< Address bit-manipulations
/**
* Return the flags which specify extensions supported by the CPU.

5
libavutil/riscv/cpu.c
View File

@ -41,7 +41,7 @@ int ff_get_cpu_flags_riscv(void)
if (hwcap & HWCAP_RV('D'))
ret |= AV_CPU_FLAG_RVD;
if (hwcap & HWCAP_RV('B'))
ret |= AV_CPU_FLAG_RVB_BASIC;
ret |= AV_CPU_FLAG_RVB_ADDR | AV_CPU_FLAG_RVB_BASIC;
/* The V extension implies all Zve* functional subsets */
if (hwcap & HWCAP_RV('V'))
@ -59,6 +59,9 @@ int ff_get_cpu_flags_riscv(void)
#endif
#endif
#ifdef __riscv_zba
ret |= AV_CPU_FLAG_RVB_ADDR;
#endif
#ifdef __riscv_zbb
ret |= AV_CPU_FLAG_RVB_BASIC;
#endif

2
libavutil/riscv/fixed_dsp_init.c
View File

@ -32,7 +32,7 @@ av_cold void ff_fixed_dsp_init_riscv(AVFixedDSPContext *fdsp)
#if HAVE_RVV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVV_I32)
if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR))
fdsp->butterflies_fixed = ff_butterflies_fixed_rvv;
#endif
}

30
libavutil/riscv/float_dsp_init.c
View File

@ -52,21 +52,23 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
#if HAVE_RVV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVV_F32) {
fdsp->vector_fmul = ff_vector_fmul_rvv;
fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_rvv;
fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
fdsp->vector_fmul_window = ff_vector_fmul_window_rvv;
fdsp->vector_fmul_add = ff_vector_fmul_add_rvv;
fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_rvv;
fdsp->butterflies_float = ff_butterflies_float_rvv;
fdsp->scalarproduct_float = ff_scalarproduct_float_rvv;
}
if (flags & AV_CPU_FLAG_RVB_ADDR) {
if (flags & AV_CPU_FLAG_RVV_F32) {
fdsp->vector_fmul = ff_vector_fmul_rvv;
fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_rvv;
fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
fdsp->vector_fmul_window = ff_vector_fmul_window_rvv;
fdsp->vector_fmul_add = ff_vector_fmul_add_rvv;
fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_rvv;
fdsp->butterflies_float = ff_butterflies_float_rvv;
fdsp->scalarproduct_float = ff_scalarproduct_float_rvv;
}
if (flags & AV_CPU_FLAG_RVV_F64) {
fdsp->vector_dmul = ff_vector_dmul_rvv;
fdsp->vector_dmac_scalar = ff_vector_dmac_scalar_rvv;
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
if (flags & AV_CPU_FLAG_RVV_F64) {
fdsp->vector_dmul = ff_vector_dmul_rvv;
fdsp->vector_dmac_scalar = ff_vector_dmac_scalar_rvv;
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
}
}
#endif
}

2
libswscale/riscv/rgb2rgb.c
View File

@ -45,7 +45,7 @@ av_cold void rgb2rgb_init_riscv(void)
#if HAVE_RVV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVV_I32) {
if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
shuffle_bytes_0321 = ff_shuffle_bytes_0321_rvv;
shuffle_bytes_2103 = ff_shuffle_bytes_2103_rvv;
shuffle_bytes_1230 = ff_shuffle_bytes_1230_rvv;

1
tests/checkasm/checkasm.c
View File

@ -248,6 +248,7 @@ static const struct {
{ "RVI", "rvi", AV_CPU_FLAG_RVI },
{ "RVF", "rvf", AV_CPU_FLAG_RVF },
{ "RVD", "rvd", AV_CPU_FLAG_RVD },
{ "RVBaddr", "rvb_a", AV_CPU_FLAG_RVB_ADDR },
{ "RVBbasic", "rvb_b", AV_CPU_FLAG_RVB_BASIC },
{ "RVVi32", "rvv_i32", AV_CPU_FLAG_RVV_I32 },
{ "RVVf32", "rvv_f32", AV_CPU_FLAG_RVV_F32 },