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lavu/floatdsp: RISC-V V vector_dmul_scalar

This commit is contained in:
Rémi Denis-Courmont 2022-09-26 17:52:29 +03:00 committed by Lynne
parent a6c10d05fe
commit 89b7ec65a8
2 changed files with 23 additions and 0 deletions
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6
libavutil/riscv/float_dsp_init.c
View File

@ -28,6 +28,9 @@
void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
int len);
void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
int len);
av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
{
#if HAVE_RVV
@ -35,5 +38,8 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
if (flags & AV_CPU_FLAG_RVV_F32)
fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
if (flags & AV_CPU_FLAG_RVV_F64)
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
#endif
}

17
libavutil/riscv/float_dsp_rvv.S
View File

@ -37,3 +37,20 @@ NOHWF mv a2, a3
ret
endfunc
// (a0) = (a1) * fa0 [0..a2-1]
func ff_vector_dmul_scalar_rvv, zve64d
NOHWD fmv.d.x fa0, a2
NOHWD mv a2, a3
1:
vsetvli t0, a2, e64, m1, ta, ma
vle64.v v16, (a1)
sub a2, a2, t0
vfmul.vf v16, v16, fa0
sh3add a1, t0, a1
vse64.v v16, (a0)
sh3add a0, t0, a0
bnez a2, 1b
ret
endfunc