mirror of https://github.com/yuzu-emu/yuzu
565 lines
20 KiB
C++
565 lines
20 KiB
C++
// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <cinttypes>
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#include <memory>
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#include <dynarmic/interface/A64/a64.h>
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#include <dynarmic/interface/A64/config.h>
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#include "common/assert.h"
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#include "common/literals.h"
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#include "common/logging/log.h"
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#include "common/page_table.h"
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#include "common/settings.h"
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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#include "core/arm/dynarmic/arm_exclusive_monitor.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/debugger/debugger.h"
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#include "core/hardware_properties.h"
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#include "core/hle/kernel/k_process.h"
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#include "core/hle/kernel/svc.h"
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#include "core/memory.h"
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namespace Core {
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using Vector = Dynarmic::A64::Vector;
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using namespace Common::Literals;
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class DynarmicCallbacks64 : public Dynarmic::A64::UserCallbacks {
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public:
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explicit DynarmicCallbacks64(ARM_Dynarmic_64& parent_)
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: parent{parent_}, memory(parent.system.ApplicationMemory()),
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debugger_enabled{parent.system.DebuggerEnabled()},
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check_memory_access{debugger_enabled ||
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!Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
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u8 MemoryRead8(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Read);
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return memory.Read8(vaddr);
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}
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u16 MemoryRead16(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Read);
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return memory.Read16(vaddr);
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}
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u32 MemoryRead32(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Read);
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return memory.Read32(vaddr);
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}
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u64 MemoryRead64(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Read);
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return memory.Read64(vaddr);
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}
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Vector MemoryRead128(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Read);
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return {memory.Read64(vaddr), memory.Read64(vaddr + 8)};
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}
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std::optional<u32> MemoryReadCode(u64 vaddr) override {
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if (!memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
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return std::nullopt;
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}
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return memory.Read32(vaddr);
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}
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void MemoryWrite8(u64 vaddr, u8 value) override {
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if (CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write)) {
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memory.Write8(vaddr, value);
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}
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}
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void MemoryWrite16(u64 vaddr, u16 value) override {
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if (CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write)) {
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memory.Write16(vaddr, value);
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}
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}
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void MemoryWrite32(u64 vaddr, u32 value) override {
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if (CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write)) {
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memory.Write32(vaddr, value);
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}
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}
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void MemoryWrite64(u64 vaddr, u64 value) override {
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if (CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write)) {
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memory.Write64(vaddr, value);
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}
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}
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void MemoryWrite128(u64 vaddr, Vector value) override {
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if (CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write)) {
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memory.Write64(vaddr, value[0]);
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memory.Write64(vaddr + 8, value[1]);
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}
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}
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bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, std::uint8_t expected) override {
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return CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write) &&
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memory.WriteExclusive8(vaddr, value, expected);
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}
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bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, std::uint16_t expected) override {
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return CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write) &&
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memory.WriteExclusive16(vaddr, value, expected);
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}
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bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, std::uint32_t expected) override {
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return CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write) &&
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memory.WriteExclusive32(vaddr, value, expected);
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}
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bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, std::uint64_t expected) override {
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return CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write) &&
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memory.WriteExclusive64(vaddr, value, expected);
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}
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bool MemoryWriteExclusive128(u64 vaddr, Vector value, Vector expected) override {
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return CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write) &&
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memory.WriteExclusive128(vaddr, value, expected);
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}
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void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
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parent.LogBacktrace();
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LOG_ERROR(Core_ARM,
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"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, memory.Read32(pc));
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ReturnException(pc, ARM_Interface::no_execute);
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}
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void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
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u64 value) override {
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switch (op) {
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case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
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static constexpr u64 ICACHE_LINE_SIZE = 64;
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const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
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parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
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break;
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}
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
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parent.system.InvalidateCpuInstructionCaches();
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break;
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
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default:
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LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
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break;
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}
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parent.jit.load()->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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switch (exception) {
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case Dynarmic::A64::Exception::WaitForInterrupt:
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case Dynarmic::A64::Exception::WaitForEvent:
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case Dynarmic::A64::Exception::SendEvent:
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case Dynarmic::A64::Exception::SendEventLocal:
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case Dynarmic::A64::Exception::Yield:
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return;
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case Dynarmic::A64::Exception::NoExecuteFault:
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LOG_CRITICAL(Core_ARM, "Cannot execute instruction at unmapped address {:#016x}", pc);
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ReturnException(pc, ARM_Interface::no_execute);
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return;
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default:
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if (debugger_enabled) {
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ReturnException(pc, ARM_Interface::breakpoint);
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return;
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}
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parent.LogBacktrace();
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LOG_CRITICAL(Core_ARM, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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static_cast<std::size_t>(exception), pc, memory.Read32(pc));
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}
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}
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void CallSVC(u32 swi) override {
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parent.svc_swi = swi;
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parent.jit.load()->HaltExecution(ARM_Interface::svc_call);
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}
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void AddTicks(u64 ticks) override {
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if (parent.uses_wall_clock) {
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return;
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}
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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// if not all cores are doing a similar amount of work. Instead of doing this, we should
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// device a way so that timing is consistent across all cores without increasing the ticks 4
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// times.
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u64 amortized_ticks = ticks / Core::Hardware::NUM_CPU_CORES;
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// Always execute at least one tick.
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amortized_ticks = std::max<u64>(amortized_ticks, 1);
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parent.system.CoreTiming().AddTicks(amortized_ticks);
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}
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u64 GetTicksRemaining() override {
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if (parent.uses_wall_clock) {
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if (!IsInterrupted()) {
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return minimum_run_cycles;
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}
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return 0U;
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}
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return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
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}
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u64 GetCNTPCT() override {
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return parent.system.CoreTiming().GetClockTicks();
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}
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bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) {
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if (!check_memory_access) {
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return true;
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}
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if (!memory.IsValidVirtualAddressRange(addr, size)) {
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LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
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addr);
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parent.jit.load()->HaltExecution(ARM_Interface::no_execute);
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return false;
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}
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if (!debugger_enabled) {
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return true;
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}
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const auto match{parent.MatchingWatchpoint(addr, size, type)};
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if (match) {
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parent.halted_watchpoint = match;
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parent.jit.load()->HaltExecution(ARM_Interface::watchpoint);
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return false;
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}
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return true;
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}
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void ReturnException(u64 pc, Dynarmic::HaltReason hr) {
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parent.SaveContext(parent.breakpoint_context);
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parent.breakpoint_context.pc = pc;
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parent.jit.load()->HaltExecution(hr);
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}
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bool IsInterrupted() {
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return parent.system.Kernel().PhysicalCore(parent.core_index).IsInterrupted();
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}
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ARM_Dynarmic_64& parent;
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Core::Memory::Memory& memory;
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u64 tpidrro_el0 = 0;
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u64 tpidr_el0 = 0;
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const bool debugger_enabled{};
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const bool check_memory_access{};
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static constexpr u64 minimum_run_cycles = 10000U;
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};
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std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable* page_table,
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std::size_t address_space_bits) const {
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Dynarmic::A64::UserConfig config;
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// Callbacks
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config.callbacks = cb.get();
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// Memory
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if (page_table) {
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config.page_table = reinterpret_cast<void**>(page_table->pointers.data());
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config.page_table_address_space_bits = address_space_bits;
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config.page_table_pointer_mask_bits = Common::PageTable::ATTRIBUTE_BITS;
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config.silently_mirror_page_table = false;
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config.absolute_offset_page_table = true;
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config.detect_misaligned_access_via_page_table = 16 | 32 | 64 | 128;
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config.only_detect_misalignment_via_page_table_on_page_boundary = true;
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config.fastmem_pointer = page_table->fastmem_arena;
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config.fastmem_address_space_bits = address_space_bits;
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config.silently_mirror_fastmem = false;
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config.fastmem_exclusive_access = config.fastmem_pointer != nullptr;
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config.recompile_on_exclusive_fastmem_failure = true;
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}
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// Multi-process state
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config.processor_id = core_index;
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config.global_monitor = &exclusive_monitor.monitor;
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// System registers
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config.tpidrro_el0 = &cb->tpidrro_el0;
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config.tpidr_el0 = &cb->tpidr_el0;
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config.dczid_el0 = 4;
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config.ctr_el0 = 0x8444c004;
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config.cntfrq_el0 = Hardware::CNTFREQ;
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// Unpredictable instructions
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config.define_unpredictable_behaviour = true;
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// Timing
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config.wall_clock_cntpct = uses_wall_clock;
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config.enable_cycle_counting = true;
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// Code cache size
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#ifdef ARCHITECTURE_arm64
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config.code_cache_size = 128_MiB;
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#else
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config.code_cache_size = 512_MiB;
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#endif
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// Allow memory fault handling to work
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if (system.DebuggerEnabled()) {
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config.check_halt_on_memory_access = true;
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}
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// null_jit
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if (!page_table) {
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// Don't waste too much memory on null_jit
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config.code_cache_size = 8_MiB;
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}
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// Safe optimizations
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if (Settings::values.cpu_debug_mode) {
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if (!Settings::values.cpuopt_page_tables) {
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config.page_table = nullptr;
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}
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if (!Settings::values.cpuopt_block_linking) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::BlockLinking;
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}
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if (!Settings::values.cpuopt_return_stack_buffer) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::ReturnStackBuffer;
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}
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if (!Settings::values.cpuopt_fast_dispatcher) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::FastDispatch;
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}
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if (!Settings::values.cpuopt_context_elimination) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::GetSetElimination;
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}
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if (!Settings::values.cpuopt_const_prop) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::ConstProp;
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}
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if (!Settings::values.cpuopt_misc_ir) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::MiscIROpt;
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}
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if (!Settings::values.cpuopt_reduce_misalign_checks) {
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config.only_detect_misalignment_via_page_table_on_page_boundary = false;
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}
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if (!Settings::values.cpuopt_fastmem) {
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config.fastmem_pointer = nullptr;
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config.fastmem_exclusive_access = false;
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}
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if (!Settings::values.cpuopt_fastmem_exclusives) {
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config.fastmem_exclusive_access = false;
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}
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if (!Settings::values.cpuopt_recompile_exclusives) {
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config.recompile_on_exclusive_fastmem_failure = false;
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}
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if (!Settings::values.cpuopt_ignore_memory_aborts) {
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config.check_halt_on_memory_access = true;
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}
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} else {
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// Unsafe optimizations
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if (Settings::values.cpu_accuracy.GetValue() == Settings::CPUAccuracy::Unsafe) {
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config.unsafe_optimizations = true;
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if (Settings::values.cpuopt_unsafe_unfuse_fma) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_UnfuseFMA;
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}
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if (Settings::values.cpuopt_unsafe_reduce_fp_error) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_ReducedErrorFP;
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}
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if (Settings::values.cpuopt_unsafe_inaccurate_nan) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_InaccurateNaN;
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}
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if (Settings::values.cpuopt_unsafe_fastmem_check) {
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config.fastmem_address_space_bits = 64;
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}
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if (Settings::values.cpuopt_unsafe_ignore_global_monitor) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_IgnoreGlobalMonitor;
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}
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}
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// Curated optimizations
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if (Settings::values.cpu_accuracy.GetValue() == Settings::CPUAccuracy::Auto) {
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config.unsafe_optimizations = true;
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_UnfuseFMA;
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config.fastmem_address_space_bits = 64;
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_IgnoreGlobalMonitor;
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}
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// Paranoia mode for debugging optimizations
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if (Settings::values.cpu_accuracy.GetValue() == Settings::CPUAccuracy::Paranoid) {
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config.unsafe_optimizations = false;
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config.optimizations = Dynarmic::no_optimizations;
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}
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}
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return std::make_shared<Dynarmic::A64::Jit>(config);
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}
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Dynarmic::HaltReason ARM_Dynarmic_64::RunJit() {
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return jit.load()->Run();
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}
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Dynarmic::HaltReason ARM_Dynarmic_64::StepJit() {
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return jit.load()->Step();
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}
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u32 ARM_Dynarmic_64::GetSvcNumber() const {
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return svc_swi;
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}
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const Kernel::DebugWatchpoint* ARM_Dynarmic_64::HaltedWatchpoint() const {
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return halted_watchpoint;
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}
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void ARM_Dynarmic_64::RewindBreakpointInstruction() {
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LoadContext(breakpoint_context);
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}
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ARM_Dynarmic_64::ARM_Dynarmic_64(System& system_, bool uses_wall_clock_,
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ExclusiveMonitor& exclusive_monitor_, std::size_t core_index_)
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: ARM_Interface{system_, uses_wall_clock_},
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cb(std::make_unique<DynarmicCallbacks64>(*this)), core_index{core_index_},
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exclusive_monitor{dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor_)},
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null_jit{MakeJit(nullptr, 48)}, jit{null_jit.get()} {}
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ARM_Dynarmic_64::~ARM_Dynarmic_64() = default;
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void ARM_Dynarmic_64::SetPC(u64 pc) {
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jit.load()->SetPC(pc);
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}
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u64 ARM_Dynarmic_64::GetPC() const {
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return jit.load()->GetPC();
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}
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u64 ARM_Dynarmic_64::GetSP() const {
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return jit.load()->GetSP();
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}
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u64 ARM_Dynarmic_64::GetReg(int index) const {
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return jit.load()->GetRegister(index);
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}
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void ARM_Dynarmic_64::SetReg(int index, u64 value) {
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jit.load()->SetRegister(index, value);
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}
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u128 ARM_Dynarmic_64::GetVectorReg(int index) const {
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return jit.load()->GetVector(index);
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}
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void ARM_Dynarmic_64::SetVectorReg(int index, u128 value) {
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jit.load()->SetVector(index, value);
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}
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u32 ARM_Dynarmic_64::GetPSTATE() const {
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return jit.load()->GetPstate();
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}
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void ARM_Dynarmic_64::SetPSTATE(u32 pstate) {
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jit.load()->SetPstate(pstate);
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}
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u64 ARM_Dynarmic_64::GetTlsAddress() const {
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return cb->tpidrro_el0;
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}
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void ARM_Dynarmic_64::SetTlsAddress(u64 address) {
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cb->tpidrro_el0 = address;
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}
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u64 ARM_Dynarmic_64::GetTPIDR_EL0() const {
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return cb->tpidr_el0;
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}
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void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
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cb->tpidr_el0 = value;
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}
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void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
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Dynarmic::A64::Jit* j = jit.load();
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ctx.cpu_registers = j->GetRegisters();
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ctx.sp = j->GetSP();
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ctx.pc = j->GetPC();
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ctx.pstate = j->GetPstate();
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ctx.vector_registers = j->GetVectors();
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ctx.fpcr = j->GetFpcr();
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ctx.fpsr = j->GetFpsr();
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ctx.tpidr = cb->tpidr_el0;
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}
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|
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void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
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Dynarmic::A64::Jit* j = jit.load();
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j->SetRegisters(ctx.cpu_registers);
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j->SetSP(ctx.sp);
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|
j->SetPC(ctx.pc);
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|
j->SetPstate(ctx.pstate);
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j->SetVectors(ctx.vector_registers);
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|
j->SetFpcr(ctx.fpcr);
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j->SetFpsr(ctx.fpsr);
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SetTPIDR_EL0(ctx.tpidr);
|
|
}
|
|
|
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void ARM_Dynarmic_64::SignalInterrupt() {
|
|
jit.load()->HaltExecution(break_loop);
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|
}
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|
|
|
void ARM_Dynarmic_64::ClearInterrupt() {
|
|
jit.load()->ClearHalt(break_loop);
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|
}
|
|
|
|
void ARM_Dynarmic_64::ClearInstructionCache() {
|
|
jit.load()->ClearCache();
|
|
}
|
|
|
|
void ARM_Dynarmic_64::InvalidateCacheRange(u64 addr, std::size_t size) {
|
|
jit.load()->InvalidateCacheRange(addr, size);
|
|
}
|
|
|
|
void ARM_Dynarmic_64::ClearExclusiveState() {
|
|
jit.load()->ClearExclusiveState();
|
|
}
|
|
|
|
void ARM_Dynarmic_64::PageTableChanged(Common::PageTable& page_table,
|
|
std::size_t new_address_space_size_in_bits) {
|
|
ThreadContext64 ctx{};
|
|
SaveContext(ctx);
|
|
|
|
auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
|
|
auto iter = jit_cache.find(key);
|
|
if (iter != jit_cache.end()) {
|
|
jit.store(iter->second.get());
|
|
LoadContext(ctx);
|
|
return;
|
|
}
|
|
std::shared_ptr new_jit = MakeJit(&page_table, new_address_space_size_in_bits);
|
|
jit.store(new_jit.get());
|
|
LoadContext(ctx);
|
|
jit_cache.emplace(key, std::move(new_jit));
|
|
}
|
|
|
|
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_64::GetBacktrace(Core::System& system,
|
|
u64 fp, u64 lr, u64 pc) {
|
|
std::vector<BacktraceEntry> out;
|
|
auto& memory = system.ApplicationMemory();
|
|
|
|
out.push_back({"", 0, pc, 0, ""});
|
|
|
|
// fp (= x29) points to the previous frame record.
|
|
// Frame records are two words long:
|
|
// fp+0 : pointer to previous frame record
|
|
// fp+8 : value of lr for frame
|
|
for (size_t i = 0; i < 256; i++) {
|
|
out.push_back({"", 0, lr, 0, ""});
|
|
if (!fp || (fp % 4 != 0) || !memory.IsValidVirtualAddressRange(fp, 16)) {
|
|
break;
|
|
}
|
|
lr = memory.Read64(fp + 8);
|
|
fp = memory.Read64(fp);
|
|
}
|
|
|
|
SymbolicateBacktrace(system, out);
|
|
|
|
return out;
|
|
}
|
|
|
|
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_64::GetBacktraceFromContext(
|
|
System& system, const ThreadContext64& ctx) {
|
|
const auto& reg = ctx.cpu_registers;
|
|
return GetBacktrace(system, reg[29], reg[30], ctx.pc);
|
|
}
|
|
|
|
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_64::GetBacktrace() const {
|
|
return GetBacktrace(system, GetReg(29), GetReg(30), GetPC());
|
|
}
|
|
|
|
} // namespace Core
|