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https://github.com/mpv-player/mpv
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988281c471
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@17368 b3059339-0415-0410-9bf9-f77b7e298cf2
413 lines
16 KiB
C
413 lines
16 KiB
C
/**
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SiS register definitions and access macros.
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From SiS X11 driver.
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Copyright 2001-2003 by Thomas Winischhofer, Vienna, Austria.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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**/
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#ifndef VIDIX_SIS_REGS_H
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#define VIDIX_SIS_REGS_H
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#define inSISREG(base) INPORT8(base)
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#define outSISREG(base,val) OUTPORT8(base, val)
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#define orSISREG(base,val) do { \
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unsigned char __Temp = INPORT8(base); \
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outSISREG(base, __Temp | (val)); \
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} while (0)
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#define andSISREG(base,val) do { \
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unsigned char __Temp = INPORT8(base); \
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outSISREG(base, __Temp & (val)); \
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} while (0)
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#define inSISIDXREG(base,idx,var) do { \
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OUTPORT8(base, idx); var=INPORT8((base)+1); \
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} while (0)
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#define outSISIDXREG(base,idx,val) do { \
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OUTPORT8(base, idx); OUTPORT8((base)+1, val); \
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} while (0)
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#define orSISIDXREG(base,idx,val) do { \
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unsigned char __Temp; \
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OUTPORT8(base, idx); \
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__Temp = INPORT8((base)+1)|(val); \
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outSISIDXREG(base,idx,__Temp); \
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} while (0)
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#define andSISIDXREG(base,idx,and) do { \
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unsigned char __Temp; \
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OUTPORT8(base, idx); \
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__Temp = INPORT8((base)+1)&(and); \
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outSISIDXREG(base,idx,__Temp); \
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} while (0)
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#define setSISIDXREG(base,idx,and,or) do { \
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unsigned char __Temp; \
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OUTPORT8(base, idx); \
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__Temp = (INPORT8((base)+1)&(and))|(or); \
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outSISIDXREG(base,idx,__Temp); \
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} while (0)
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#define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l))
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#define GENMASK(mask) BITMASK(1?mask,0?mask)
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#define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask))
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#define SETBITS(val,mask) ((val) << (0?mask))
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#define SETBIT(n) (1<<(n))
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#define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to))
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#define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \
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GETBITSTR(val,from,to))
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#define GETVAR8(var) ((var)&0xFF)
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#define SETVAR8(var,val) (var) = GETVAR8(val)
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/* #define VGA_RELIO_BASE 0x380 */
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#define AROFFSET 0x40 /* VGA_ATTR_INDEX - VGA_RELIO_BASE */
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#define ARROFFSET 0x41 /* VGA_ATTR_DATA_R - VGA_RELIO_BASE */
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#define GROFFSET 0x4e /* VGA_GRAPH_INDEX - VGA_RELIO_BASE */
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#define SROFFSET 0x44 /* VGA_SEQ_INDEX - VGA_RELIO_BASE */
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#define CROFFSET 0x54 /* VGA_CRTC_INDEX_OFFSET + VGA_IOBASE_COLOR - VGA_RELIO_BASE */
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#define MISCROFFSET 0x4c /* VGA_MISC_OUT_R - VGA_RELIO_BASE */
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#define MISCWOFFSET 0x42 /* VGA_MISC_OUT_W - VGA_RELIO_BASE */
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#define INPUTSTATOFFSET 0x5A
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#define PART1OFFSET 0x04
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#define PART2OFFSET 0x10
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#define PART3OFFSET 0x12
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#define PART4OFFSET 0x14
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#define PART5OFFSET 0x16
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#define VIDEOOFFSET 0x02
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#define COLREGOFFSET 0x48
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#define SIS_IOBASE sis_iobase /* var defined in sis_vid.c */
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#define SISAR SIS_IOBASE + AROFFSET
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#define SISARR SIS_IOBASE + ARROFFSET
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#define SISGR SIS_IOBASE + GROFFSET
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#define SISSR SIS_IOBASE + SROFFSET
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#define SISCR SIS_IOBASE + CROFFSET
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#define SISMISCR SIS_IOBASE + MISCROFFSET
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#define SISMISCW SIS_IOBASE + MISCWOFFSET
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#define SISINPSTAT SIS_IOBASE + INPUTSTATOFFSET
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#define SISPART1 SIS_IOBASE + PART1OFFSET
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#define SISPART2 SIS_IOBASE + PART2OFFSET
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#define SISPART3 SIS_IOBASE + PART3OFFSET
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#define SISPART4 SIS_IOBASE + PART4OFFSET
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#define SISPART5 SIS_IOBASE + PART5OFFSET
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#define SISVID SIS_IOBASE + VIDEOOFFSET
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#define SISCOLIDX SIS_IOBASE + COLREGOFFSET
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#define SISCOLDATA SIS_IOBASE + COLREGOFFSET + 1
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#define SISCOL2IDX SISPART5
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#define SISCOL2DATA SISPART5 + 1
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#define vc_index_offset 0x00 /* Video capture - unused */
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#define vc_data_offset 0x01
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#define vi_index_offset VIDEOOFFSET
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#define vi_data_offset (VIDEOOFFSET + 1)
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#define crt2_index_offset PART1OFFSET
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#define crt2_port_offset (PART1OFFSET + 1)
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#define sr_index_offset SROFFSET
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#define sr_data_offset (SROFFSET + 1)
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#define cr_index_offset CROFFSET
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#define cr_data_offset (CROFFSET + 1)
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#define input_stat INPUTSTATOFFSET
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/* For old chipsets (5597/5598, 6326, 530/620) ------------ */
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/* SR (3C4) */
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#define BankReg 0x06
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#define ClockReg 0x07
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#define CPUThreshold 0x08
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#define CRTThreshold 0x09
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#define CRTCOff 0x0A
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#define DualBanks 0x0B
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#define MMIOEnable 0x0B
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#define RAMSize 0x0C
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#define Mode64 0x0C
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#define ExtConfStatus1 0x0E
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#define ClockBase 0x13
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#define LinearAdd0 0x20
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#define LinearAdd1 0x21
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#define GraphEng 0x27
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#define MemClock0 0x28
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#define MemClock1 0x29
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#define XR2A 0x2A
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#define XR2B 0x2B
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#define TurboQueueBase 0x2C
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#define FBSize 0x2F
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#define ExtMiscCont5 0x34
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#define ExtMiscCont9 0x3C
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/* 3x4 */
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#define Offset 0x13
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/* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 */
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/* VGA standard register */
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#define Index_SR_Graphic_Mode 0x06
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#define Index_SR_RAMDAC_Ctrl 0x07
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#define Index_SR_Threshold_Ctrl1 0x08
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#define Index_SR_Threshold_Ctrl2 0x09
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#define Index_SR_Misc_Ctrl 0x0F
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#define Index_SR_DDC 0x11
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#define Index_SR_Feature_Connector_Ctrl 0x12
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#define Index_SR_DRAM_Sizing 0x14
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#define Index_SR_DRAM_State_Machine_Ctrl 0x15
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#define Index_SR_AGP_PCI_State_Machine 0x21
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#define Index_SR_Internal_MCLK0 0x28
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#define Index_SR_Internal_MCLK1 0x29
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#define Index_SR_Internal_DCLK1 0x2B
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#define Index_SR_Internal_DCLK2 0x2C
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#define Index_SR_Internal_DCLK3 0x2D
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#define Index_SR_Ext_Clock_Sel 0x32
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#define Index_SR_Int_Status 0x34
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#define Index_SR_Int_Enable 0x35
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#define Index_SR_Int_Reset 0x36
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#define Index_SR_Power_On_Trap 0x38
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#define Index_SR_Power_On_Trap2 0x39
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#define Index_SR_Power_On_Trap3 0x3A
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/* video registers (300/630/730/315/550/650/740 only) */
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#define Index_VI_Passwd 0x00
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/* Video overlay horizontal start/end, unit=screen pixels */
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#define Index_VI_Win_Hor_Disp_Start_Low 0x01
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#define Index_VI_Win_Hor_Disp_End_Low 0x02
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#define Index_VI_Win_Hor_Over 0x03 /* Overflow */
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/* Video overlay vertical start/end, unit=screen pixels */
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#define Index_VI_Win_Ver_Disp_Start_Low 0x04
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#define Index_VI_Win_Ver_Disp_End_Low 0x05
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#define Index_VI_Win_Ver_Over 0x06 /* Overflow */
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/* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */
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#define Index_VI_Disp_Y_Buf_Start_Low 0x07
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#define Index_VI_Disp_Y_Buf_Start_Middle 0x08
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#define Index_VI_Disp_Y_Buf_Start_High 0x09
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/* U Plane (4:2:0) buffer start address, unit=word */
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#define Index_VI_U_Buf_Start_Low 0x0A
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#define Index_VI_U_Buf_Start_Middle 0x0B
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#define Index_VI_U_Buf_Start_High 0x0C
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/* V Plane (4:2:0) buffer start address, unit=word */
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#define Index_VI_V_Buf_Start_Low 0x0D
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#define Index_VI_V_Buf_Start_Middle 0x0E
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#define Index_VI_V_Buf_Start_High 0x0F
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/* Pitch for Y, UV Planes, unit=word */
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#define Index_VI_Disp_Y_Buf_Pitch_Low 0x10
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#define Index_VI_Disp_UV_Buf_Pitch_Low 0x11
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#define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12
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/* What is this ? */
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#define Index_VI_Disp_Y_Buf_Preset_Low 0x13
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#define Index_VI_Disp_Y_Buf_Preset_Middle 0x14
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#define Index_VI_UV_Buf_Preset_Low 0x15
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#define Index_VI_UV_Buf_Preset_Middle 0x16
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#define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17
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/* Scaling control registers */
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#define Index_VI_Hor_Post_Up_Scale_Low 0x18
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#define Index_VI_Hor_Post_Up_Scale_High 0x19
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#define Index_VI_Ver_Up_Scale_Low 0x1A
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#define Index_VI_Ver_Up_Scale_High 0x1B
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#define Index_VI_Scale_Control 0x1C
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/* Playback line buffer control */
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#define Index_VI_Play_Threshold_Low 0x1D
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#define Index_VI_Play_Threshold_High 0x1E
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#define Index_VI_Line_Buffer_Size 0x1F
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/* Destination color key */
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#define Index_VI_Overlay_ColorKey_Red_Min 0x20
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#define Index_VI_Overlay_ColorKey_Green_Min 0x21
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#define Index_VI_Overlay_ColorKey_Blue_Min 0x22
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#define Index_VI_Overlay_ColorKey_Red_Max 0x23
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#define Index_VI_Overlay_ColorKey_Green_Max 0x24
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#define Index_VI_Overlay_ColorKey_Blue_Max 0x25
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/* Source color key, YUV color space */
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#define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26
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#define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27
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#define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28
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#define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29
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#define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A
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#define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B
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/* Contrast enhancement and brightness control */
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#define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */
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#define Index_VI_Brightness 0x2D
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#define Index_VI_Contrast_Enh_Ctrl 0x2E
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#define Index_VI_Key_Overlay_OP 0x2F
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#define Index_VI_Control_Misc0 0x30
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#define Index_VI_Control_Misc1 0x31
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#define Index_VI_Control_Misc2 0x32
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/* TW: Subpicture registers */
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#define Index_VI_SubPict_Buf_Start_Low 0x33
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#define Index_VI_SubPict_Buf_Start_Middle 0x34
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#define Index_VI_SubPict_Buf_Start_High 0x35
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/* TW: What is this ? */
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#define Index_VI_SubPict_Buf_Preset_Low 0x36
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#define Index_VI_SubPict_Buf_Preset_Middle 0x37
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/* TW: Subpicture pitch, unit=16 bytes */
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#define Index_VI_SubPict_Buf_Pitch 0x38
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/* TW: Subpicture scaling control */
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#define Index_VI_SubPict_Hor_Scale_Low 0x39
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#define Index_VI_SubPict_Hor_Scale_High 0x3A
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#define Index_VI_SubPict_Vert_Scale_Low 0x3B
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#define Index_VI_SubPict_Vert_Scale_High 0x3C
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#define Index_VI_SubPict_Scale_Control 0x3D
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/* (0x40 = enable/disable subpicture) */
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/* TW: Subpicture line buffer control */
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#define Index_VI_SubPict_Threshold 0x3E
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/* TW: What is this? */
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#define Index_VI_FIFO_Max 0x3F
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/* TW: Subpicture palette; 16 colors, total 32 bytes address space */
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#define Index_VI_SubPict_Pal_Base_Low 0x40
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#define Index_VI_SubPict_Pal_Base_High 0x41
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/* I wish I knew how to use these ... */
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#define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */
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#define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */
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#define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */
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#define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */
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/* TW: MPEG AutoFlip scale */
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#define Index_MPEG_Ver_Up_Scale_Low 0x64
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#define Index_MPEG_Ver_Up_Scale_High 0x65
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#define Index_MPEG_Y_Buf_Preset_Low 0x66
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#define Index_MPEG_Y_Buf_Preset_Middle 0x67
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#define Index_MPEG_UV_Buf_Preset_Low 0x68
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#define Index_MPEG_UV_Buf_Preset_Middle 0x69
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#define Index_MPEG_Y_UV_Buf_Preset_High 0x6A
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/* TW: The following registers only exist on the 310/325 series */
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/* TW: Bit 16:24 of Y_U_V buf start address (?) */
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#define Index_VI_Y_Buf_Start_Over 0x6B
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#define Index_VI_U_Buf_Start_Over 0x6C
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#define Index_VI_V_Buf_Start_Over 0x6D
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#define Index_VI_Disp_Y_Buf_Pitch_High 0x6E
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#define Index_VI_Disp_UV_Buf_Pitch_High 0x6F
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/* Hue and saturation */
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#define Index_VI_Hue 0x70
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#define Index_VI_Saturation 0x71
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#define Index_VI_SubPict_Start_Over 0x72
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#define Index_VI_SubPict_Buf_Pitch_High 0x73
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#define Index_VI_Control_Misc3 0x74
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/* TW: Bits (and helpers) for Index_VI_Control_Misc0 */
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#define VI_Misc0_Enable_Overlay 0x02
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#define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */
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#define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */
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#define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */
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#define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (YUY2) */
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#define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */
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/* TW: Bits for Index_VI_Control_Misc1 */
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/* #define VI_Misc1_? 0x01 */
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#define VI_Misc1_BOB_Enable 0x02
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#define VI_Misc1_Line_Merge 0x04
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#define VI_Misc1_Field_Mode 0x08
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/* #define VI_Misc1_? 0x10 */
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#define VI_Misc1_Non_Interleave 0x20 /* 300 series only? */
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#define VI_Misc1_Buf_Addr_Lock 0x20 /* 310 series only? */
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/* #define VI_Misc1_? 0x40 */
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/* #define VI_Misc1_? 0x80 */
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/* TW: Bits for Index_VI_Control_Misc2 */
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#define VI_Misc2_Select_Video2 0x01
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#define VI_Misc2_Video2_On_Top 0x02
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/* #define VI_Misc2_? 0x04 */
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#define VI_Misc2_Vertical_Interpol 0x08
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#define VI_Misc2_Dual_Line_Merge 0x10
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#define VI_Misc2_All_Line_Merge 0x20 /* 310 series only? */
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#define VI_Misc2_Auto_Flip_Enable 0x40 /* 300 series only? */
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#define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 310 series only? */
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/* TW: Bits for Index_VI_Control_Misc3 */
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#define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */
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#define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */
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#define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */
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/* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */
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#define VI_ROP_Never 0x00
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#define VI_ROP_DestKey 0x03
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#define VI_ROP_Always 0x0F
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/*
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* CRT_2 function control register ---------------------------------
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*/
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#define Index_CRT2_FC_CONTROL 0x00
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#define Index_CRT2_FC_SCREEN_HIGH 0x04
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#define Index_CRT2_FC_SCREEN_MID 0x05
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#define Index_CRT2_FC_SCREEN_LOW 0x06
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#define Index_CRT2_FC_ENABLE_WRITE 0x24
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#define Index_CRT2_FC_VR 0x25
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#define Index_CRT2_FC_VCount 0x27
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#define Index_CRT2_FC_VCount1 0x28
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#define Index_310_CRT2_FC_VR 0x30 /* d[1] = vertical retrace */
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#define Index_310_CRT2_FC_RT 0x33 /* d[7] = retrace in progress */
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/* video attributes - these should probably be configurable on the fly
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* so users with different desktop sizes can keep
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* captured data off the desktop
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*/
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#define _VINWID 704
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#define _VINHGT _VINHGT_NTSC
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#define _VINHGT_NTSC 240
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#define _VINHGT_PAL 290
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#define _VIN_WINDOW (704 * 291 * 2)
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#define _VBI_WINDOW (704 * 64 * 2)
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#define _VIN_FIELD_EVEN 1
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#define _VIN_FIELD_ODD 2
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#define _VIN_FIELD_BOTH 4
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/* i2c registers (TW; not on 300/310/325 series) */
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#define X_INDEXREG 0x14
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#define X_PORTREG 0x15
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#define X_DATA 0x0f
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#define I2C_SCL 0x00
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#define I2C_SDA 0x01
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#define I2C_DELAY 10
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/* mmio registers for video */
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#define REG_PRIM_CRT_COUNTER 0x8514
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/* TW: MPEG MMIO registers (630 and later) ----------------------------*/
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/* Not public (yet?) */
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#endif /* VIDIX_SIS_REGS_H */
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