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https://github.com/mpv-player/mpv
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More configurable stuff
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@3251 b3059339-0415-0410-9bf9-f77b7e298cf2
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nick
parent
8d73b46405
commit
ec56759d68
@ -14,7 +14,7 @@
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* Also here was used code from CVS of GATOS project and X11 trees.
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*/
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#define RADEON_VID_VERSION "1.0.0"
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#define RADEON_VID_VERSION "1.0.1"
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/*
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It's entirely possible this major conflicts with something else
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@ -29,9 +29,7 @@
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Highest priority: fbvid.h compatibility
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High priority: RGB/BGR 2-32, YVU9, IF09 support
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Middle priority:
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OV0_COLOUR_CNTL brightness saturation
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SCALER_GAMMA_SEL_BRIGHT gamma correction ???
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OV0_GRAPHICS_KEY_CLR color key
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OV0_AUTO_FLIP_CNTL
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OV0_FILTER_CNTL
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OV0_VIDEO_KEY_CLR
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@ -130,12 +128,16 @@ typedef struct bes_registers_s
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uint32_t exclusive_horz;
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uint32_t auto_flip_cntl;
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uint32_t filter_cntl;
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int brightness;
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int saturation;
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uint32_t graphics_key_msk;
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uint32_t graphics_key_clr;
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uint32_t key_cntl;
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uint32_t test;
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/* Configurable stuff */
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int double_buff;
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int brightness;
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int saturation;
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uint32_t graphics_key_clr;
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int deinterlace_on;
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uint32_t deinterlace_pattern;
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} bes_registers_t;
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typedef struct video_registers_s
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@ -187,7 +189,6 @@ static uint32_t radeon_vid_in_use = 0;
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static uint8_t *radeon_mmio_base = 0;
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static uint32_t radeon_mem_base = 0;
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static int32_t radeon_overlay_off = 0;
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static int radeon_double_buff=1;
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static uint32_t radeon_ram_size = 0;
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static mga_vid_config_t radeon_config;
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@ -276,13 +277,6 @@ static void radeon_vid_stop_video( void )
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OUTREG(OV0_EXCLUSIVE_HORZ, 0);
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OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */
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OUTREG(OV0_FILTER_CNTL, 0x0000000f);
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/*
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OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
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(saturation << 8) |
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(saturation << 16));
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OUTREG(OV0_GRAPHICS_KEY_MSK, (1 << depth) - 1);
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OUTREG(OV0_GRAPHICS_KEY_CLR, colorKey);
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*/
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OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE);
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OUTREG(OV0_TEST, 0);
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}
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@ -303,7 +297,7 @@ RTRACE(RVID_MSG"OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n
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OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
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OUTREG(OV0_DEINTERLACE_PATTERN,0x900AAAAA);
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OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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@ -335,10 +329,10 @@ RTRACE(RVID_MSG"OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n
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OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init);
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bes_flags = SCALER_ENABLE |
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SCALER_ADAPTIVE_DEINT |
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SCALER_SMART_SWITCH |
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SCALER_HORZ_PICK_NEAREST;
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if(radeon_double_buff) bes_flags |= SCALER_DOUBLE_BUFFER;
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if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER;
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if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT;
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#ifdef RAGE128
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bes_flags |= SCALER_BURST_PER_PLANE;
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#endif
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@ -366,16 +360,6 @@ RTRACE(RVID_MSG"OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n
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}
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RTRACE(RVID_MSG"OV0: SCALER=%x\n",bes_flags);
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OUTREG(OV0_SCALE_CNTL, bes_flags);
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/*
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TODO:
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brightness: -64 : +63
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saturation: 0 : 31
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OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
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(saturation << 8) |
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(saturation << 16));
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OUTREG(OV0_GRAPHICS_KEY_CLR, colkey_red | colkey_green << 8 | colkey_blue << 16);
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*/
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OUTREG(OV0_REG_LOAD_CNTL, 0);
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}
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@ -550,7 +534,7 @@ RTRACE(RVID_MSG"BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n"
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static void radeon_vid_frame_sel(int frame)
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{
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uint32_t off0,off1,off2;
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if(!radeon_double_buff) return;
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if(!besr.double_buff) return;
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if(frame%2)
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{
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off0 = besr.vid_buf3_base_adrs;
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@ -571,12 +555,23 @@ static void radeon_vid_frame_sel(int frame)
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OUTREG(OV0_REG_LOAD_CNTL, 0);
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}
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static void radeon_vid_make_default(void)
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{
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besr.deinterlace_pattern = 0x900AAAAA;
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OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
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besr.deinterlace_on=1;
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besr.double_buff=1;
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}
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static void radeon_vid_preset(void)
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{
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unsigned tmp;
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tmp = INREG(OV0_COLOUR_CNTL);
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besr.saturation = (tmp>>8)&0x1f;
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besr.brightness = tmp & 0x7f;
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besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR);
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besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN);
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}
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static int video_on = 0;
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@ -777,6 +772,9 @@ static int radeon_vid_config_card(void)
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#define PARAM_BRIGHTNESS "brightness="
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#define PARAM_SATURATION "saturation="
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#define PARAM_DOUBLE_BUFF "double_buff="
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#define PARAM_COLOUR_KEY "colour_key="
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#define PARAM_DEINTERLACE "deinterlace="
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#define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern="
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static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos)
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{
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@ -787,11 +785,15 @@ static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_
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len = 0;
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len += sprintf(&buf[len],"Chip: %s\n",ati_card_ids[detected_chip].name);
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len += sprintf(&buf[len],"Memory: %p:%x\n",radeon_mem_base,radeon_ram_size*0x100000);
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len += sprintf(&buf[len],"MMIO: %p\n",radeon_mmio_base);
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len += sprintf(&buf[len],"MMIO: %p\n\n",radeon_mmio_base);
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len += sprintf(&buf[len],"Configurable stuff:\n");
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len += sprintf(&buf[len],PARAM_DOUBLE_BUFF"%s\n",radeon_double_buff?"on":"off");
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len += sprintf(&buf[len],"~~~~~~~~~~~~~~~~~~~\n");
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len += sprintf(&buf[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off");
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len += sprintf(&buf[len],PARAM_BRIGHTNESS"%i\n",brightness);
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len += sprintf(&buf[len],PARAM_SATURATION"%u\n",saturation);
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len += sprintf(&buf[len],PARAM_COLOUR_KEY"%X\n",besr.graphics_key_clr);
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len += sprintf(&buf[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off");
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len += sprintf(&buf[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern);
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return len;
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}
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@ -803,8 +805,8 @@ static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count
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brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10);
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if(brightness >= -64 && brightness <= 63)
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OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
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(besr.saturation << 8) |
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(besr.saturation << 16));
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(besr.saturation << 8) |
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(besr.saturation << 16));
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}
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else
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if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0)
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@ -813,14 +815,34 @@ static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count
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saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10);
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if(saturation >= 0 && saturation <= 31)
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OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) |
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(saturation << 8) |
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(saturation << 16));
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(saturation << 8) |
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(saturation << 16));
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}
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else
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if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0)
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{
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if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) radeon_double_buff = 1;
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else radeon_double_buff = 0;
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if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1;
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else besr.double_buff = 0;
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}
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else
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if(memcmp(buf,PARAM_COLOUR_KEY,min(count,strlen(PARAM_COLOUR_KEY))) == 0)
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{
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long ckey;
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ckey=simple_strtol(&buf[strlen(PARAM_COLOUR_KEY)],NULL,16);
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OUTREG(OV0_GRAPHICS_KEY_CLR, ckey);
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}
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else
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if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0)
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{
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if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1;
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else besr.deinterlace_on = 0;
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}
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else
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if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0)
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{
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long dpat;
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dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16);
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OUTREG(OV0_DEINTERLACE_PATTERN, dpat);
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}
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radeon_vid_preset();
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return count;
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@ -922,6 +944,7 @@ static int radeon_vid_initialize(void)
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return -EINVAL;
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}
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radeon_vid_save_state();
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radeon_vid_make_default();
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radeon_vid_preset();
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return(0);
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}
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