mirror of
https://github.com/mpv-player/mpv
synced 2025-01-01 04:36:24 +01:00
A lot of VE related improvements and code cleanup
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@1916 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick
parent
6883c2ead8
commit
70f1ff1715
@ -9,17 +9,49 @@
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#define PCI_DEVICE_ID_RADEON_QG 0x5147
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#define PCI_DEVICE_ID_RADEON_QY 0x5159
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#define PCI_DEVICE_ID_RADEON_QZ 0x515A
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#define PCI_DEVICE_ID_RADEON_LY 0x4C59
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#define PCI_DEVICE_ID_RADEON_LZ 0x4C5A
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#define PCI_DEVICE_ID_RADEON_LW 0x4C57
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#define RADEON_REGSIZE 0x4000
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#define MM_INDEX 0x0000
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/* MM_INDEX bit constants */
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# define MM_APER 0x80000000
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#define MM_DATA 0x0004
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#define BUS_CNTL 0x0030
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/* BUS_CNTL bit constants */
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# define BUS_DBL_RESYNC 0x00000001
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# define BUS_MSTR_RESET 0x00000002
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# define BUS_FLUSH_BUF 0x00000004
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# define BUS_STOP_REQ_DIS 0x00000008
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# define BUS_ROTATION_DIS 0x00000010
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# define BUS_MASTER_DIS 0x00000040
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# define BUS_ROM_WRT_EN 0x00000080
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# define BUS_DIS_ROM 0x00001000
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# define BUS_PCI_READ_RETRY_EN 0x00002000
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# define BUS_AGP_AD_STEPPING_EN 0x00004000
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# define BUS_PCI_WRT_RETRY_EN 0x00008000
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# define BUS_MSTR_RD_MULT 0x00100000
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# define BUS_MSTR_RD_LINE 0x00200000
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# define BUS_SUSPEND 0x00400000
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# define LAT_16X 0x00800000
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# define BUS_RD_DISCARD_EN 0x01000000
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# define BUS_RD_ABORT_EN 0x02000000
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# define BUS_MSTR_WS 0x04000000
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# define BUS_PARKING_DIS 0x08000000
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# define BUS_MSTR_DISCONNECT_EN 0x10000000
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# define BUS_WRT_BURST 0x20000000
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# define BUS_READ_BURST 0x40000000
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# define BUS_RDY_READ_DLY 0x80000000
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#define HI_STAT 0x004C
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#define BUS_CNTL1 0x0034
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# define BUS_WAIT_ON_LOCK_EN (1 << 4)
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#define I2C_CNTL_1 0x0094
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#define CONFIG_CNTL 0x00E0
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/* CONFIG_CNTL bit constants */
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# define CFG_VGA_RAM_EN 0x00000100
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#define CONFIG_MEMSIZE 0x00F8
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#define CONFIG_APER_0_BASE 0x0100
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#define CONFIG_APER_1_BASE 0x0104
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@ -30,6 +62,14 @@
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#define PAD_CTLR_STRENGTH 0x0168
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#define PAD_CTLR_UPDATE 0x016C
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#define AGP_CNTL 0x0174
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# define AGP_APER_SIZE_256MB (0x00 << 0)
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# define AGP_APER_SIZE_128MB (0x20 << 0)
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# define AGP_APER_SIZE_64MB (0x30 << 0)
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# define AGP_APER_SIZE_32MB (0x38 << 0)
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# define AGP_APER_SIZE_16MB (0x3c << 0)
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# define AGP_APER_SIZE_8MB (0x3e << 0)
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# define AGP_APER_SIZE_4MB (0x3f << 0)
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# define AGP_APER_SIZE_MASK (0x3f << 0)
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#define BM_STATUS 0x0160
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#define CAP0_TRIG_CNTL 0x0950
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#define VIPH_CONTROL 0x0C40
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@ -63,6 +103,10 @@
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#define PMI_DATA 0x0F57
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#define AGP_CAP_ID 0x0F58
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#define AGP_STATUS 0x0F5C
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# define AGP_1X_MODE 0x01
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# define AGP_2X_MODE 0x02
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# define AGP_4X_MODE 0x04
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# define AGP_MODE_MASK 0x07
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#define AGP_COMMAND 0x0F60
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#define AIC_CTRL 0x01D0
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#define AIC_STAT 0x01D4
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@ -72,8 +116,62 @@
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#define AIC_TLB_ADDR 0x01E4
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#define AIC_TLB_DATA 0x01E8
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#define DAC_CNTL 0x0058
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/* DAC_CNTL bit constants */
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# define DAC_8BIT_EN 0x00000100
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# define DAC_4BPP_PIX_ORDER 0x00000200
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# define DAC_CRC_EN 0x00080000
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# define DAC_MASK_ALL (0xff << 24)
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# define DAC_VGA_ADR_EN (1 << 13)
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# define DAC_RANGE_CNTL (3 << 0)
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# define DAC_BLANKING (1 << 2)
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#define DAC_CNTL2 0x007c
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/* DAC_CNTL2 bit constants */
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# define DAC2_DAC_CLK_SEL (1 << 0)
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# define DAC2_DAC2_CLK_SEL (1 << 1)
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# define DAC2_PALETTE_ACC_CTL (1 << 5)
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#define TV_DAC_CNTL 0x088c
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/* TV_DAC_CNTL bit constants */
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# define TV_DAC_STD_MASK 0x0300
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# define TV_DAC_RDACPD (1 << 24)
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# define TV_DAC_GDACPD (1 << 25)
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# define TV_DAC_BDACPD (1 << 26)
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#define CRTC_GEN_CNTL 0x0050
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/* CRTC_GEN_CNTL bit constants */
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# define CRTC_DBL_SCAN_EN 0x00000001
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# define CRTC_INTERLACE_EN (1 << 1)
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# define CRTC_CSYNC_EN (1 << 4)
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# define CRTC_CUR_EN 0x00010000
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# define CRTC_CUR_MODE_MASK (7 << 17)
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# define CRTC_ICON_EN (1 << 20)
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# define CRTC_EXT_DISP_EN (1 << 24)
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# define CRTC_EN (1 << 25)
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# define CRTC_DISP_REQ_EN_B (1 << 26)
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#define CRTC2_GEN_CNTL 0x03f8
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/* CRTC2_GEN_CNTL bit constants */
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# define CRTC2_DBL_SCAN_EN (1 << 0)
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# define CRTC2_INTERLACE_EN (1 << 1)
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# define CRTC2_SYNC_TRISTAT (1 << 4)
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# define CRTC2_HSYNC_TRISTAT (1 << 5)
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# define CRTC2_VSYNC_TRISTAT (1 << 6)
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# define CRTC2_CRT2_ON (1 << 7)
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# define CRTC2_ICON_EN (1 << 15)
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# define CRTC2_CUR_EN (1 << 16)
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# define CRTC2_CUR_MODE_MASK (7 << 20)
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# define CRTC2_DISP_DIS (1 << 23)
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# define CRTC2_EN (1 << 25)
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# define CRTC2_DISP_REQ_EN_B (1 << 26)
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# define CRTC2_HSYNC_DIS (1 << 28)
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# define CRTC2_VSYNC_DIS (1 << 29)
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#define MEM_CNTL 0x0140
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/* MEM_CNTL bit constants */
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# define MEM_CTLR_STATUS_IDLE 0x00000000
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# define MEM_CTLR_STATUS_BUSY 0x00100000
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# define MEM_SEQNCR_STATUS_IDLE 0x00000000
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# define MEM_SEQNCR_STATUS_BUSY 0x00200000
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# define MEM_ARBITER_STATUS_IDLE 0x00000000
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# define MEM_ARBITER_STATUS_BUSY 0x00400000
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# define MEM_REQ_UNLOCK 0x00000000
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# define MEM_REQ_LOCK 0x00800000
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#define EXT_MEM_CNTL 0x0144
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#define MC_AGP_LOCATION 0x014C
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#define MEM_IO_CNTL_A0 0x0178
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@ -93,6 +191,10 @@
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#define HDP_DEBUG 0x0138
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#define SW_SEMAPHORE 0x013C
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#define SURFACE_CNTL 0x0B00
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/* SURFACE_CNTL bit constants */
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# define SURF_TRANSLATION_DIS (1 << 8)
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# define NONSURF_AP0_SWP_16BPP (1 << 20)
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# define NONSURF_AP0_SWP_32BPP (2 << 20)
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#define SURFACE0_LOWER_BOUND 0x0B04
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#define SURFACE1_LOWER_BOUND 0x0B14
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#define SURFACE2_LOWER_BOUND 0x0B24
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@ -121,7 +223,23 @@
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#define SURFACE_ACCESS_CLR 0x0BFC
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#define GEN_INT_CNTL 0x0040
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#define GEN_INT_STATUS 0x0044
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# define VSYNC_INT_AK (1 << 2)
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# define VSYNC_INT (1 << 2)
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#define CRTC_EXT_CNTL 0x0054
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/* CRTC_EXT_CNTL bit constants */
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# define CRTC_VGA_XOVERSCAN (1 << 0)
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# define VGA_ATI_LINEAR 0x00000008
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# define VGA_128KAP_PAGING 0x00000010
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# define XCRT_CNT_EN (1 << 6)
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# define CRTC_HSYNC_DIS (1 << 8)
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# define CRTC_VSYNC_DIS (1 << 9)
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# define CRTC_DISPLAY_DIS (1 << 10)
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# define CRTC_SYNC_TRISTAT (1 << 11)
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# define CRTC_CRT_ON (1 << 15)
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#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055
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# define CRTC_HSYNC_DIS_BYTE (1 << 0)
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# define CRTC_VSYNC_DIS_BYTE (1 << 1)
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# define CRTC_DISPLAY_DIS_BYTE (1 << 2)
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#define RB3D_CNTL 0x1C3C
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#define WAIT_UNTIL 0x1720
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#define ISYNC_CNTL 0x1724
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@ -131,6 +249,15 @@
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#define RBBM_CNTL 0x00EC
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#define RBBM_CNTL_alt_1 0x0E44
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#define RBBM_SOFT_RESET 0x00F0
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/* RBBM_SOFT_RESET bit constants */
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# define SOFT_RESET_CP (1 << 0)
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# define SOFT_RESET_HI (1 << 1)
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# define SOFT_RESET_SE (1 << 2)
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# define SOFT_RESET_RE (1 << 3)
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# define SOFT_RESET_PP (1 << 4)
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# define SOFT_RESET_E2 (1 << 5)
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# define SOFT_RESET_RB (1 << 6)
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# define SOFT_RESET_HDP (1 << 7)
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#define RBBM_SOFT_RESET_alt_1 0x0E48
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#define NQWAIT_UNTIL 0x0E50
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#define RBBM_DEBUG 0x0E6C
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@ -139,6 +266,9 @@
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#define RBBM_CMDFIFO_DATAH 0x0E78
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#define RBBM_CMDFIFO_STAT 0x0E7C
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#define CRTC_STATUS 0x005C
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/* CRTC_STATUS bit constants */
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# define CRTC_VBLANK 0x00000001
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# define CRTC_VBLANK_SAVE (1 << 1)
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#define GPIO_VGA_DDC 0x0060
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#define GPIO_DVI_DDC 0x0064
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#define GPIO_MONID 0x0068
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@ -146,17 +276,69 @@
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#define PALETTE_DATA 0x00B4
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#define PALETTE_30_DATA 0x00B8
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#define CRTC_H_TOTAL_DISP 0x0200
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# define CRTC_H_TOTAL (0x03ff << 0)
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# define CRTC_H_TOTAL_SHIFT 0
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# define CRTC_H_DISP (0x01ff << 16)
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# define CRTC_H_DISP_SHIFT 16
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#define CRTC2_H_TOTAL_DISP 0x0300
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# define CRTC2_H_TOTAL (0x03ff << 0)
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# define CRTC2_H_TOTAL_SHIFT 0
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# define CRTC2_H_DISP (0x01ff << 16)
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# define CRTC2_H_DISP_SHIFT 16
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#define CRTC_H_SYNC_STRT_WID 0x0204
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# define CRTC_H_SYNC_STRT_PIX (0x07 << 0)
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# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
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# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3
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# define CRTC_H_SYNC_WID (0x3f << 16)
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# define CRTC_H_SYNC_WID_SHIFT 16
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# define CRTC_H_SYNC_POL (1 << 23)
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#define CRTC2_H_SYNC_STRT_WID 0x0304
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# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
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# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
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# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
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# define CRTC2_H_SYNC_WID (0x3f << 16)
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# define CRTC2_H_SYNC_WID_SHIFT 16
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# define CRTC2_H_SYNC_POL (1 << 23)
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#define CRTC_V_TOTAL_DISP 0x0208
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# define CRTC_V_TOTAL (0x07ff << 0)
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# define CRTC_V_TOTAL_SHIFT 0
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# define CRTC_V_DISP (0x07ff << 16)
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# define CRTC_V_DISP_SHIFT 16
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#define CRTC2_V_TOTAL_DISP 0x0308
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# define CRTC2_V_TOTAL (0x07ff << 0)
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# define CRTC2_V_TOTAL_SHIFT 0
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# define CRTC2_V_DISP (0x07ff << 16)
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# define CRTC2_V_DISP_SHIFT 16
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#define CRTC_V_SYNC_STRT_WID 0x020C
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# define CRTC_V_SYNC_STRT (0x7ff << 0)
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# define CRTC_V_SYNC_STRT_SHIFT 0
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# define CRTC_V_SYNC_WID (0x1f << 16)
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# define CRTC_V_SYNC_WID_SHIFT 16
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# define CRTC_V_SYNC_POL (1 << 23)
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#define CRTC2_V_SYNC_STRT_WID 0x030C
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# define CRTC2_V_SYNC_STRT (0x7ff << 0)
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# define CRTC2_V_SYNC_STRT_SHIFT 0
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# define CRTC2_V_SYNC_WID (0x1f << 16)
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# define CRTC2_V_SYNC_WID_SHIFT 16
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# define CRTC2_V_SYNC_POL (1 << 23)
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#define CRTC_VLINE_CRNT_VLINE 0x0210
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# define CRTC_CRNT_VLINE_MASK (0x7ff << 16)
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#define CRTC2_VLINE_CRNT_VLINE 0x0310
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#define CRTC_CRNT_FRAME 0x0214
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#define CRTC2_CRNT_FRAME 0x0314
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#define CRTC_GUI_TRIG_VLINE 0x0218
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#define CRTC2_GUI_TRIG_VLINE 0x0318
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#define CRTC_DEBUG 0x021C
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#define CRTC2_DEBUG 0x031C
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#define CRTC_OFFSET_RIGHT 0x0220
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#define CRTC_OFFSET 0x0224
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#define CRTC2_OFFSET 0x0324
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#define CRTC_OFFSET_CNTL 0x0228
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# define CRTC_TILE_EN (1 << 15)
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#define CRTC2_OFFSET_CNTL 0x0328
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# define CRTC2_TILE_EN (1 << 15)
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#define CRTC_PITCH 0x022C
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#define CRTC2_PITCH 0x032C
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#define OVR_CLR 0x0230
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#define OVR_WID_LEFT_RIGHT 0x0234
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#define OVR_WID_TOP_BOTTOM 0x0238
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@ -166,22 +348,68 @@
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#define N_VIF_COUNT 0x0248
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#define SNAPSHOT_VIF_COUNT 0x024C
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#define FP_CRTC_H_TOTAL_DISP 0x0250
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#define FP_CRTC2_H_TOTAL_DISP 0x0350
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#define FP_CRTC_V_TOTAL_DISP 0x0254
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#define FP_CRTC2_V_TOTAL_DISP 0x0354
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#define CRT_CRTC_H_SYNC_STRT_WID 0x0258
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#define CRT_CRTC_V_SYNC_STRT_WID 0x025C
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#define CUR_OFFSET 0x0260
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#define CUR_HORZ_VERT_POSN 0x0264
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#define CUR_HORZ_VERT_OFF 0x0268
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/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
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# define CUR_LOCK 0x80000000
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#define CUR_CLR0 0x026C
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#define CUR_CLR1 0x0270
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#define CUR2_OFFSET 0x0360
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#define CUR2_HORZ_VERT_POSN 0x0364
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#define CUR2_HORZ_VERT_OFF 0x0368
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# define CUR2_LOCK (1 << 31)
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#define CUR2_CLR0 0x036c
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#define CUR2_CLR1 0x0370
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#define FP_HORZ_VERT_ACTIVE 0x0278
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#define CRTC_MORE_CNTL 0x027C
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#define DAC_EXT_CNTL 0x0280
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#define FP_GEN_CNTL 0x0284
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/* FP_GEN_CNTL bit constants */
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# define FP_FPON (1 << 0)
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# define FP_TMDS_EN (1 << 2)
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# define FP_EN_TMDS (1 << 7)
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# define FP_DETECT_SENSE (1 << 8)
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# define FP_SEL_CRTC2 (1 << 13)
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# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
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# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
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# define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
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# define FP_CRTC_USE_SHADOW_VEND (1 << 18)
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# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
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# define FP_DFP_SYNC_SEL (1 << 21)
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# define FP_CRTC_LOCK_8DOT (1 << 22)
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# define FP_CRT_SYNC_SEL (1 << 23)
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# define FP_USE_SHADOW_EN (1 << 24)
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# define FP_CRT_SYNC_ALT (1 << 26)
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#define FP2_GEN_CNTL 0x0288
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/* FP2_GEN_CNTL bit constants */
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# define FP2_FPON (1 << 0)
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# define FP2_TMDS_EN (1 << 2)
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# define FP2_EN_TMDS (1 << 7)
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# define FP2_DETECT_SENSE (1 << 8)
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# define FP2_SEL_CRTC2 (1 << 13)
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# define FP2_FP_POL (1 << 16)
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# define FP2_LP_POL (1 << 17)
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# define FP2_SCK_POL (1 << 18)
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# define FP2_LCD_CNTL_MASK (7 << 19)
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# define FP2_PAD_FLOP_EN (1 << 22)
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# define FP2_CRC_EN (1 << 23)
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# define FP2_CRC_READ_EN (1 << 24)
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#define FP_HORZ_STRETCH 0x028C
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#define FP_VERT_STRETCH 0x0290
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#define FP_H_SYNC_STRT_WID 0x02C4
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#define FP_H2_SYNC_STRT_WID 0x03C4
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#define FP_V_SYNC_STRT_WID 0x02C8
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#define FP_V2_SYNC_STRT_WID 0x03C8
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#define FP_HORZ_STRETCH 0x028C
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#define FP_HORZ2_STRETCH 0x038C
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#define FP_VERT_STRETCH 0x0290
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#define FP_VERT2_STRETCH 0x0390
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#define AUX_WINDOW_HORZ_CNTL 0x02D8
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#define AUX_WINDOW_VERT_CNTL 0x02DC
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#define DDA_CONFIG 0x02e0
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@ -250,6 +478,7 @@
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#define SUBPIC_H_ACCUM_INIT 0x0584
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#define SUBPIC_V_ACCUM_INIT 0x0588
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#define DISP_MISC_CNTL 0x0D00
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# define SOFT_RESET_GRPH_PP (1 << 0)
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#define DAC_MACRO_CNTL 0x0D04
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#define DISP_PWR_MAN 0x0D08
|
||||
#define DISP_TEST_DEBUG_CNTL 0x0D10
|
||||
@ -270,6 +499,8 @@
|
||||
#define OV0_GAMMA_3C0_3FF 0x0D54
|
||||
#define DISP_MERGE_CNTL 0x0D60
|
||||
#define DISP_OUTPUT_CNTL 0x0D64
|
||||
# define DISP_DAC_SOURCE_MASK 0x03
|
||||
# define DISP_DAC_SOURCE_CRTC2 0x01
|
||||
#define DISP_LIN_TRANS_GRPH_A 0x0D80
|
||||
#define DISP_LIN_TRANS_GRPH_B 0x0D84
|
||||
#define DISP_LIN_TRANS_GRPH_C 0x0D88
|
||||
@ -294,6 +525,10 @@
|
||||
#define DAC_POS_SYNC_LEVEL 0x0DD4
|
||||
#define DAC_BLANK_LEVEL 0x0DD8
|
||||
#define CLOCK_CNTL_INDEX 0x0008
|
||||
/* CLOCK_CNTL_INDEX bit constants */
|
||||
# define PLL_WR_EN 0x00000080
|
||||
# define RADEON_PLL_DIV_SEL (3 << 8)
|
||||
# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
|
||||
#define CLOCK_CNTL_DATA 0x000C
|
||||
#define CP_RB_CNTL 0x0704
|
||||
#define CP_RB_BASE 0x0700
|
||||
@ -354,25 +589,169 @@
|
||||
#define SRC_SC_RIGHT 0x1654
|
||||
#define SRC_SC_BOTTOM 0x165C
|
||||
#define DP_CNTL 0x16C0
|
||||
/* DP_CNTL bit constants */
|
||||
# define DST_X_RIGHT_TO_LEFT 0x00000000
|
||||
# define DST_X_LEFT_TO_RIGHT 0x00000001
|
||||
# define DST_Y_BOTTOM_TO_TOP 0x00000000
|
||||
# define DST_Y_TOP_TO_BOTTOM 0x00000002
|
||||
# define DST_X_MAJOR 0x00000000
|
||||
# define DST_Y_MAJOR 0x00000004
|
||||
# define DST_X_TILE 0x00000008
|
||||
# define DST_Y_TILE 0x00000010
|
||||
# define DST_LAST_PEL 0x00000020
|
||||
# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
|
||||
# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
|
||||
# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
|
||||
# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
|
||||
# define DST_BRES_SIGN 0x00000100
|
||||
# define DST_HOST_BIG_ENDIAN_EN 0x00000200
|
||||
# define DST_POLYLINE_NONLAST 0x00008000
|
||||
# define DST_RASTER_STALL 0x00010000
|
||||
# define DST_POLY_EDGE 0x00040000
|
||||
#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
|
||||
/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */
|
||||
# define DST_X_MAJOR_S 0x00000000
|
||||
# define DST_Y_MAJOR_S 0x00000001
|
||||
# define DST_Y_BOTTOM_TO_TOP_S 0x00000000
|
||||
# define DST_Y_TOP_TO_BOTTOM_S 0x00008000
|
||||
# define DST_X_RIGHT_TO_LEFT_S 0x00000000
|
||||
# define DST_X_LEFT_TO_RIGHT_S 0x80000000
|
||||
#define DP_DATATYPE 0x16C4
|
||||
/* DP_DATATYPE bit constants */
|
||||
# define DST_8BPP 0x00000002
|
||||
# define DST_15BPP 0x00000003
|
||||
# define DST_16BPP 0x00000004
|
||||
# define DST_24BPP 0x00000005
|
||||
# define DST_32BPP 0x00000006
|
||||
# define DST_8BPP_RGB332 0x00000007
|
||||
# define DST_8BPP_Y8 0x00000008
|
||||
# define DST_8BPP_RGB8 0x00000009
|
||||
# define DST_16BPP_VYUY422 0x0000000b
|
||||
# define DST_16BPP_YVYU422 0x0000000c
|
||||
# define DST_32BPP_AYUV444 0x0000000e
|
||||
# define DST_16BPP_ARGB4444 0x0000000f
|
||||
# define BRUSH_SOLIDCOLOR 0x00000d00
|
||||
# define SRC_MONO 0x00000000
|
||||
# define SRC_MONO_LBKGD 0x00010000
|
||||
# define SRC_DSTCOLOR 0x00030000
|
||||
# define BYTE_ORDER_MSB_TO_LSB 0x00000000
|
||||
# define BYTE_ORDER_LSB_TO_MSB 0x40000000
|
||||
# define DP_CONVERSION_TEMP 0x80000000
|
||||
# define HOST_BIG_ENDIAN_EN (1 << 29)
|
||||
#define DP_MIX 0x16C8
|
||||
/* DP_MIX bit constants */
|
||||
# define DP_SRC_RECT 0x00000200
|
||||
# define DP_SRC_HOST 0x00000300
|
||||
# define DP_SRC_HOST_BYTEALIGN 0x00000400
|
||||
#define DP_WRITE_MSK 0x16CC
|
||||
#define DP_XOP 0x17F8
|
||||
#define CLR_CMP_CLR_SRC 0x15C4
|
||||
#define CLR_CMP_CLR_DST 0x15C8
|
||||
#define CLR_CMP_CNTL 0x15C0
|
||||
/* CLR_CMP_CNTL bit constants */
|
||||
# define COMPARE_SRC_FALSE 0x00000000
|
||||
# define COMPARE_SRC_TRUE 0x00000001
|
||||
# define COMPARE_SRC_NOT_EQUAL 0x00000004
|
||||
# define COMPARE_SRC_EQUAL 0x00000005
|
||||
# define COMPARE_SRC_EQUAL_FLIP 0x00000007
|
||||
# define COMPARE_DST_FALSE 0x00000000
|
||||
# define COMPARE_DST_TRUE 0x00000100
|
||||
# define COMPARE_DST_NOT_EQUAL 0x00000400
|
||||
# define COMPARE_DST_EQUAL 0x00000500
|
||||
# define COMPARE_DESTINATION 0x00000000
|
||||
# define COMPARE_SOURCE 0x01000000
|
||||
# define COMPARE_SRC_AND_DST 0x02000000
|
||||
#define CLR_CMP_MSK 0x15CC
|
||||
#define DSTCACHE_MODE 0x1710
|
||||
#define DSTCACHE_CTLSTAT 0x1714
|
||||
/* DSTCACHE_CTLSTAT bit constants */
|
||||
# define RB2D_DC_FLUSH (3 << 0)
|
||||
# define RB2D_DC_FLUSH_ALL 0xf
|
||||
# define RB2D_DC_BUSY (1 << 31)
|
||||
#define DEFAULT_PITCH_OFFSET 0x16E0
|
||||
#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
|
||||
/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
|
||||
# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
|
||||
# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
|
||||
#define DP_GUI_MASTER_CNTL 0x146C
|
||||
/* DP_GUI_MASTER_CNTL bit constants */
|
||||
# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
|
||||
# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
|
||||
# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
|
||||
# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
|
||||
# define GMC_SRC_CLIP_DEFAULT 0x00000000
|
||||
# define GMC_SRC_CLIP_LEAVE 0x00000004
|
||||
# define GMC_DST_CLIP_DEFAULT 0x00000000
|
||||
# define GMC_DST_CLIP_LEAVE 0x00000008
|
||||
# define GMC_BRUSH_8x8MONO 0x00000000
|
||||
# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
|
||||
# define GMC_BRUSH_8x1MONO 0x00000020
|
||||
# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
|
||||
# define GMC_BRUSH_1x8MONO 0x00000040
|
||||
# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
|
||||
# define GMC_BRUSH_32x1MONO 0x00000060
|
||||
# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
|
||||
# define GMC_BRUSH_32x32MONO 0x00000080
|
||||
# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
|
||||
# define GMC_BRUSH_8x8COLOR 0x000000a0
|
||||
# define GMC_BRUSH_8x1COLOR 0x000000b0
|
||||
# define GMC_BRUSH_1x8COLOR 0x000000c0
|
||||
# define GMC_BRUSH_SOLID_COLOR 0x000000d0
|
||||
# define GMC_DST_8BPP 0x00000200
|
||||
# define GMC_DST_15BPP 0x00000300
|
||||
# define GMC_DST_16BPP 0x00000400
|
||||
# define GMC_DST_24BPP 0x00000500
|
||||
# define GMC_DST_32BPP 0x00000600
|
||||
# define GMC_DST_8BPP_RGB332 0x00000700
|
||||
# define GMC_DST_8BPP_Y8 0x00000800
|
||||
# define GMC_DST_8BPP_RGB8 0x00000900
|
||||
# define GMC_DST_16BPP_VYUY422 0x00000b00
|
||||
# define GMC_DST_16BPP_YVYU422 0x00000c00
|
||||
# define GMC_DST_32BPP_AYUV444 0x00000e00
|
||||
# define GMC_DST_16BPP_ARGB4444 0x00000f00
|
||||
# define GMC_SRC_MONO 0x00000000
|
||||
# define GMC_SRC_MONO_LBKGD 0x00001000
|
||||
# define GMC_SRC_DSTCOLOR 0x00003000
|
||||
# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
|
||||
# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
|
||||
# define GMC_DP_CONVERSION_TEMP_9300 0x00008000
|
||||
# define GMC_DP_CONVERSION_TEMP_6500 0x00000000
|
||||
# define GMC_DP_SRC_RECT 0x02000000
|
||||
# define GMC_DP_SRC_HOST 0x03000000
|
||||
# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
|
||||
# define GMC_3D_FCN_EN_CLR 0x00000000
|
||||
# define GMC_3D_FCN_EN_SET 0x08000000
|
||||
# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
|
||||
# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
|
||||
# define GMC_AUX_CLIP_LEAVE 0x00000000
|
||||
# define GMC_AUX_CLIP_CLEAR 0x20000000
|
||||
# define GMC_WRITE_MASK_LEAVE 0x00000000
|
||||
# define GMC_WRITE_MASK_SET 0x40000000
|
||||
# define GMC_CLR_CMP_CNTL_DIS (1 << 28)
|
||||
# define GMC_SRC_DATATYPE_COLOR (3 << 12)
|
||||
# define ROP3_S 0x00cc0000
|
||||
# define ROP3_SRCCOPY 0x00cc0000
|
||||
# define ROP3_P 0x00f00000
|
||||
# define ROP3_PATCOPY 0x00f00000
|
||||
# define DP_SRC_SOURCE_MASK (7 << 24)
|
||||
# define GMC_BRUSH_NONE (15 << 4)
|
||||
# define DP_SRC_SOURCE_MEMORY (2 << 24)
|
||||
# define GMC_BRUSH_SOLIDCOLOR 0x000000d0
|
||||
#define SC_TOP_LEFT 0x16EC
|
||||
#define SC_BOTTOM_RIGHT 0x16F0
|
||||
#define SRC_SC_BOTTOM_RIGHT 0x16F4
|
||||
#define RB2D_DSTCACHE_CTLSTAT 0x342C
|
||||
|
||||
#define RADEON_BASE_CODE 0x0f0b
|
||||
#define RADEON_BIOS_0_SCRATCH 0x0010
|
||||
#define RADEON_BIOS_1_SCRATCH 0x0014
|
||||
#define RADEON_BIOS_2_SCRATCH 0x0018
|
||||
#define RADEON_BIOS_3_SCRATCH 0x001c
|
||||
#define RADEON_BIOS_4_SCRATCH 0x0020
|
||||
#define RADEON_BIOS_5_SCRATCH 0x0024
|
||||
#define RADEON_BIOS_6_SCRATCH 0x0028
|
||||
#define RADEON_BIOS_7_SCRATCH 0x002c
|
||||
|
||||
|
||||
#define CLK_PIN_CNTL 0x0001
|
||||
#define PPLL_CNTL 0x0002
|
||||
@ -389,267 +768,16 @@
|
||||
#define SCLK_CNTL 0x000d
|
||||
#define MPLL_CNTL 0x000e
|
||||
#define MCLK_CNTL 0x0012
|
||||
/* MCLK_CNTL bit constants */
|
||||
# define FORCEON_MCLKA (1 << 16)
|
||||
# define FORCEON_MCLKB (1 << 17)
|
||||
# define FORCEON_YCLKA (1 << 18)
|
||||
# define FORCEON_YCLKB (1 << 19)
|
||||
# define FORCEON_MC (1 << 20)
|
||||
# define FORCEON_AIC (1 << 21)
|
||||
#define AGP_PLL_CNTL 0x000b
|
||||
#define PLL_TEST_CNTL 0x0013
|
||||
|
||||
|
||||
/* MCLK_CNTL bit constants */
|
||||
#define FORCEON_MCLKA (1 << 16)
|
||||
#define FORCEON_MCLKB (1 << 17)
|
||||
#define FORCEON_YCLKA (1 << 18)
|
||||
#define FORCEON_YCLKB (1 << 19)
|
||||
#define FORCEON_MC (1 << 20)
|
||||
#define FORCEON_AIC (1 << 21)
|
||||
|
||||
|
||||
/* BUS_CNTL bit constants */
|
||||
#define BUS_DBL_RESYNC 0x00000001
|
||||
#define BUS_MSTR_RESET 0x00000002
|
||||
#define BUS_FLUSH_BUF 0x00000004
|
||||
#define BUS_STOP_REQ_DIS 0x00000008
|
||||
#define BUS_ROTATION_DIS 0x00000010
|
||||
#define BUS_MASTER_DIS 0x00000040
|
||||
#define BUS_ROM_WRT_EN 0x00000080
|
||||
#define BUS_DIS_ROM 0x00001000
|
||||
#define BUS_PCI_READ_RETRY_EN 0x00002000
|
||||
#define BUS_AGP_AD_STEPPING_EN 0x00004000
|
||||
#define BUS_PCI_WRT_RETRY_EN 0x00008000
|
||||
#define BUS_MSTR_RD_MULT 0x00100000
|
||||
#define BUS_MSTR_RD_LINE 0x00200000
|
||||
#define BUS_SUSPEND 0x00400000
|
||||
#define LAT_16X 0x00800000
|
||||
#define BUS_RD_DISCARD_EN 0x01000000
|
||||
#define BUS_RD_ABORT_EN 0x02000000
|
||||
#define BUS_MSTR_WS 0x04000000
|
||||
#define BUS_PARKING_DIS 0x08000000
|
||||
#define BUS_MSTR_DISCONNECT_EN 0x10000000
|
||||
#define BUS_WRT_BURST 0x20000000
|
||||
#define BUS_READ_BURST 0x40000000
|
||||
#define BUS_RDY_READ_DLY 0x80000000
|
||||
|
||||
|
||||
/* CLOCK_CNTL_INDEX bit constants */
|
||||
#define PLL_WR_EN 0x00000080
|
||||
|
||||
/* CONFIG_CNTL bit constants */
|
||||
#define CFG_VGA_RAM_EN 0x00000100
|
||||
|
||||
/* CRTC_EXT_CNTL bit constants */
|
||||
#define VGA_ATI_LINEAR 0x00000008
|
||||
#define VGA_128KAP_PAGING 0x00000010
|
||||
#define XCRT_CNT_EN (1 << 6)
|
||||
#define CRTC_HSYNC_DIS (1 << 8)
|
||||
#define CRTC_VSYNC_DIS (1 << 9)
|
||||
#define CRTC_DISPLAY_DIS (1 << 10)
|
||||
|
||||
|
||||
/* DSTCACHE_CTLSTAT bit constants */
|
||||
#define RB2D_DC_FLUSH (3 << 0)
|
||||
#define RB2D_DC_FLUSH_ALL 0xf
|
||||
#define RB2D_DC_BUSY (1 << 31)
|
||||
|
||||
|
||||
/* CRTC_GEN_CNTL bit constants */
|
||||
#define CRTC_DBL_SCAN_EN 0x00000001
|
||||
#define CRTC_CUR_EN 0x00010000
|
||||
#define CRTC_EXT_DISP_EN (1 << 24)
|
||||
#define CRTC_EN (1 << 25)
|
||||
|
||||
/* CRTC_STATUS bit constants */
|
||||
#define CRTC_VBLANK 0x00000001
|
||||
|
||||
/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
|
||||
#define CUR_LOCK 0x80000000
|
||||
|
||||
/* DAC_CNTL bit constants */
|
||||
#define DAC_8BIT_EN 0x00000100
|
||||
#define DAC_4BPP_PIX_ORDER 0x00000200
|
||||
#define DAC_CRC_EN 0x00080000
|
||||
#define DAC_MASK_ALL (0xff << 24)
|
||||
#define DAC_VGA_ADR_EN (1 << 13)
|
||||
#define DAC_RANGE_CNTL (3 << 0)
|
||||
#define DAC_BLANKING (1 << 2)
|
||||
|
||||
/* GEN_RESET_CNTL bit constants */
|
||||
#define SOFT_RESET_GUI 0x00000001
|
||||
#define SOFT_RESET_VCLK 0x00000100
|
||||
#define SOFT_RESET_PCLK 0x00000200
|
||||
#define SOFT_RESET_ECP 0x00000400
|
||||
#define SOFT_RESET_DISPENG_XCLK 0x00000800
|
||||
|
||||
/* MEM_CNTL bit constants */
|
||||
#define MEM_CTLR_STATUS_IDLE 0x00000000
|
||||
#define MEM_CTLR_STATUS_BUSY 0x00100000
|
||||
#define MEM_SEQNCR_STATUS_IDLE 0x00000000
|
||||
#define MEM_SEQNCR_STATUS_BUSY 0x00200000
|
||||
#define MEM_ARBITER_STATUS_IDLE 0x00000000
|
||||
#define MEM_ARBITER_STATUS_BUSY 0x00400000
|
||||
#define MEM_REQ_UNLOCK 0x00000000
|
||||
#define MEM_REQ_LOCK 0x00800000
|
||||
|
||||
|
||||
/* SURFACE_CNTL bit constants */
|
||||
#define SURF_TRANSLATION_DIS (1 << 8)
|
||||
#define NONSURF_AP0_SWP_16BPP (1 << 20)
|
||||
#define NONSURF_AP0_SWP_32BPP (2 << 20)
|
||||
|
||||
|
||||
/* RBBM_SOFT_RESET bit constants */
|
||||
#define SOFT_RESET_CP (1 << 0)
|
||||
#define SOFT_RESET_HI (1 << 1)
|
||||
#define SOFT_RESET_SE (1 << 2)
|
||||
#define SOFT_RESET_RE (1 << 3)
|
||||
#define SOFT_RESET_PP (1 << 4)
|
||||
#define SOFT_RESET_E2 (1 << 5)
|
||||
#define SOFT_RESET_RB (1 << 6)
|
||||
#define SOFT_RESET_HDP (1 << 7)
|
||||
|
||||
|
||||
/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
|
||||
#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
|
||||
#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
|
||||
|
||||
/* MM_INDEX bit constants */
|
||||
#define MM_APER 0x80000000
|
||||
|
||||
/* CLR_CMP_CNTL bit constants */
|
||||
#define COMPARE_SRC_FALSE 0x00000000
|
||||
#define COMPARE_SRC_TRUE 0x00000001
|
||||
#define COMPARE_SRC_NOT_EQUAL 0x00000004
|
||||
#define COMPARE_SRC_EQUAL 0x00000005
|
||||
#define COMPARE_SRC_EQUAL_FLIP 0x00000007
|
||||
#define COMPARE_DST_FALSE 0x00000000
|
||||
#define COMPARE_DST_TRUE 0x00000100
|
||||
#define COMPARE_DST_NOT_EQUAL 0x00000400
|
||||
#define COMPARE_DST_EQUAL 0x00000500
|
||||
#define COMPARE_DESTINATION 0x00000000
|
||||
#define COMPARE_SOURCE 0x01000000
|
||||
#define COMPARE_SRC_AND_DST 0x02000000
|
||||
|
||||
|
||||
/* DP_CNTL bit constants */
|
||||
#define DST_X_RIGHT_TO_LEFT 0x00000000
|
||||
#define DST_X_LEFT_TO_RIGHT 0x00000001
|
||||
#define DST_Y_BOTTOM_TO_TOP 0x00000000
|
||||
#define DST_Y_TOP_TO_BOTTOM 0x00000002
|
||||
#define DST_X_MAJOR 0x00000000
|
||||
#define DST_Y_MAJOR 0x00000004
|
||||
#define DST_X_TILE 0x00000008
|
||||
#define DST_Y_TILE 0x00000010
|
||||
#define DST_LAST_PEL 0x00000020
|
||||
#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
|
||||
#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
|
||||
#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
|
||||
#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
|
||||
#define DST_BRES_SIGN 0x00000100
|
||||
#define DST_HOST_BIG_ENDIAN_EN 0x00000200
|
||||
#define DST_POLYLINE_NONLAST 0x00008000
|
||||
#define DST_RASTER_STALL 0x00010000
|
||||
#define DST_POLY_EDGE 0x00040000
|
||||
|
||||
|
||||
/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
|
||||
#define DST_X_MAJOR_S 0x00000000
|
||||
#define DST_Y_MAJOR_S 0x00000001
|
||||
#define DST_Y_BOTTOM_TO_TOP_S 0x00000000
|
||||
#define DST_Y_TOP_TO_BOTTOM_S 0x00008000
|
||||
#define DST_X_RIGHT_TO_LEFT_S 0x00000000
|
||||
#define DST_X_LEFT_TO_RIGHT_S 0x80000000
|
||||
|
||||
|
||||
/* DP_DATATYPE bit constants */
|
||||
#define DST_8BPP 0x00000002
|
||||
#define DST_15BPP 0x00000003
|
||||
#define DST_16BPP 0x00000004
|
||||
#define DST_24BPP 0x00000005
|
||||
#define DST_32BPP 0x00000006
|
||||
#define DST_8BPP_RGB332 0x00000007
|
||||
#define DST_8BPP_Y8 0x00000008
|
||||
#define DST_8BPP_RGB8 0x00000009
|
||||
#define DST_16BPP_VYUY422 0x0000000b
|
||||
#define DST_16BPP_YVYU422 0x0000000c
|
||||
#define DST_32BPP_AYUV444 0x0000000e
|
||||
#define DST_16BPP_ARGB4444 0x0000000f
|
||||
#define BRUSH_SOLIDCOLOR 0x00000d00
|
||||
#define SRC_MONO 0x00000000
|
||||
#define SRC_MONO_LBKGD 0x00010000
|
||||
#define SRC_DSTCOLOR 0x00030000
|
||||
#define BYTE_ORDER_MSB_TO_LSB 0x00000000
|
||||
#define BYTE_ORDER_LSB_TO_MSB 0x40000000
|
||||
#define DP_CONVERSION_TEMP 0x80000000
|
||||
#define HOST_BIG_ENDIAN_EN (1 << 29)
|
||||
|
||||
|
||||
/* DP_GUI_MASTER_CNTL bit constants */
|
||||
#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
|
||||
#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
|
||||
#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
|
||||
#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
|
||||
#define GMC_SRC_CLIP_DEFAULT 0x00000000
|
||||
#define GMC_SRC_CLIP_LEAVE 0x00000004
|
||||
#define GMC_DST_CLIP_DEFAULT 0x00000000
|
||||
#define GMC_DST_CLIP_LEAVE 0x00000008
|
||||
#define GMC_BRUSH_8x8MONO 0x00000000
|
||||
#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
|
||||
#define GMC_BRUSH_8x1MONO 0x00000020
|
||||
#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
|
||||
#define GMC_BRUSH_1x8MONO 0x00000040
|
||||
#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
|
||||
#define GMC_BRUSH_32x1MONO 0x00000060
|
||||
#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
|
||||
#define GMC_BRUSH_32x32MONO 0x00000080
|
||||
#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
|
||||
#define GMC_BRUSH_8x8COLOR 0x000000a0
|
||||
#define GMC_BRUSH_8x1COLOR 0x000000b0
|
||||
#define GMC_BRUSH_1x8COLOR 0x000000c0
|
||||
#define GMC_BRUSH_SOLID_COLOR 0x000000d0
|
||||
#define GMC_DST_8BPP 0x00000200
|
||||
#define GMC_DST_15BPP 0x00000300
|
||||
#define GMC_DST_16BPP 0x00000400
|
||||
#define GMC_DST_24BPP 0x00000500
|
||||
#define GMC_DST_32BPP 0x00000600
|
||||
#define GMC_DST_8BPP_RGB332 0x00000700
|
||||
#define GMC_DST_8BPP_Y8 0x00000800
|
||||
#define GMC_DST_8BPP_RGB8 0x00000900
|
||||
#define GMC_DST_16BPP_VYUY422 0x00000b00
|
||||
#define GMC_DST_16BPP_YVYU422 0x00000c00
|
||||
#define GMC_DST_32BPP_AYUV444 0x00000e00
|
||||
#define GMC_DST_16BPP_ARGB4444 0x00000f00
|
||||
#define GMC_SRC_MONO 0x00000000
|
||||
#define GMC_SRC_MONO_LBKGD 0x00001000
|
||||
#define GMC_SRC_DSTCOLOR 0x00003000
|
||||
#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
|
||||
#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
|
||||
#define GMC_DP_CONVERSION_TEMP_9300 0x00008000
|
||||
#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
|
||||
#define GMC_DP_SRC_RECT 0x02000000
|
||||
#define GMC_DP_SRC_HOST 0x03000000
|
||||
#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
|
||||
#define GMC_3D_FCN_EN_CLR 0x00000000
|
||||
#define GMC_3D_FCN_EN_SET 0x08000000
|
||||
#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
|
||||
#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
|
||||
#define GMC_AUX_CLIP_LEAVE 0x00000000
|
||||
#define GMC_AUX_CLIP_CLEAR 0x20000000
|
||||
#define GMC_WRITE_MASK_LEAVE 0x00000000
|
||||
#define GMC_WRITE_MASK_SET 0x40000000
|
||||
#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
|
||||
#define GMC_SRC_DATATYPE_COLOR (3 << 12)
|
||||
#define ROP3_S 0x00cc0000
|
||||
#define ROP3_SRCCOPY 0x00cc0000
|
||||
#define ROP3_P 0x00f00000
|
||||
#define ROP3_PATCOPY 0x00f00000
|
||||
#define DP_SRC_SOURCE_MASK (7 << 24)
|
||||
#define GMC_BRUSH_NONE (15 << 4)
|
||||
#define DP_SRC_SOURCE_MEMORY (2 << 24)
|
||||
#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
|
||||
|
||||
/* DP_MIX bit constants */
|
||||
#define DP_SRC_RECT 0x00000200
|
||||
#define DP_SRC_HOST 0x00000300
|
||||
#define DP_SRC_HOST_BYTEALIGN 0x00000400
|
||||
|
||||
|
||||
/* masks */
|
||||
|
||||
#define CONFIG_MEMSIZE_MASK 0x1f000000
|
||||
@ -669,5 +797,12 @@
|
||||
|
||||
#define GUI_ACTIVE 0x80000000
|
||||
|
||||
/* GEN_RESET_CNTL bit constants */
|
||||
#define SOFT_RESET_GUI 0x00000001
|
||||
#define SOFT_RESET_VCLK 0x00000100
|
||||
#define SOFT_RESET_PCLK 0x00000200
|
||||
#define SOFT_RESET_ECP 0x00000400
|
||||
#define SOFT_RESET_DISPENG_XCLK 0x00000800
|
||||
|
||||
#endif /* _RADEON_H */
|
||||
|
||||
|
||||
@ -11,8 +11,6 @@
|
||||
* 2001-02-19 mode bug fixes, 0.0.7
|
||||
* 2001-07-05 fixed scrolling issues, engine initialization,
|
||||
* and minor mode tweaking, 0.0.9
|
||||
* 2001-09-06 console switching fixes, blanking fixes,
|
||||
* 0.1.0
|
||||
*
|
||||
* 2001-09-07 Radeon VE support
|
||||
* 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru>
|
||||
@ -26,14 +24,32 @@
|
||||
* 2001-09-13 merge Ani Joshi radeonfb-0.1.0:
|
||||
* console switching fixes, blanking fixes,
|
||||
* 0.1.0-ve.0
|
||||
* 2001-09-18 Radeon VE, M6 support (by Nick Kurshev <nickols_k@mail.ru>),
|
||||
* Fixed bug of rom bios detection on VE (by NK),
|
||||
* Minor code cleanup (by NK),
|
||||
* Enable CRT port on VE (by NK),
|
||||
* Disable SURFACE_CNTL because mplayer doesn't work
|
||||
* propertly (by NK)
|
||||
* 0.1.0-ve.1
|
||||
*
|
||||
* Special thanks to ATI DevRel team for their hardware donations.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#define RADEON_VERSION "0.1.0-ve.0"
|
||||
* LIMITATIONS: on dualhead Radeons (VE, M6, M7) driver doesn't work in
|
||||
* dual monitor configuration. TVout is not supported too. M7 chips currently
|
||||
* are not supported (Need volunteers to test its work). Probably these bugs
|
||||
* can be solved by importing XFree86 code, which has ATI's support.
|
||||
*
|
||||
* Mini-HOWTO: This driver doesn't accept any options. It only switches your
|
||||
* video card to graphics mode. Standard way to change video modes and other
|
||||
* video attributes is using 'fbset' utility.
|
||||
* Sample:
|
||||
*
|
||||
* #!/bin/sh
|
||||
* fbset -fb /dev/fb0 -xres 640 -yres 480 -depth 32 -vxres 640 -vyres 480 -left 70 -right 50 -upper 70 -lower 70 -laced false -pixclock 39767
|
||||
*
|
||||
*/
|
||||
|
||||
#define RADEON_VERSION "0.1.0-ve.1"
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
@ -78,9 +94,39 @@ enum radeon_chips {
|
||||
RADEON_QF,
|
||||
RADEON_QG,
|
||||
RADEON_QY,
|
||||
RADEON_QZ
|
||||
RADEON_QZ,
|
||||
RADEON_LY,
|
||||
RADEON_LZ,
|
||||
RADEON_LW
|
||||
};
|
||||
|
||||
enum radeon_montype
|
||||
{
|
||||
MT_NONE,
|
||||
MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */
|
||||
MT_LCD, /* Liquid Crystal Display */
|
||||
MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */
|
||||
MT_CTV, /* Composite TV out (not in VE) */
|
||||
MT_STV /* S-Video TV out (probably in VE only) */
|
||||
};
|
||||
|
||||
enum radeon_ddctype
|
||||
{
|
||||
DDC_NONE_DETECTED,
|
||||
DDC_MONID,
|
||||
DDC_DVI,
|
||||
DDC_VGA,
|
||||
DDC_CRT2
|
||||
};
|
||||
|
||||
enum radeon_connectortype
|
||||
{
|
||||
CONNECTOR_NONE,
|
||||
CONNECTOR_PROPRIETARY,
|
||||
CONNECTOR_CRT,
|
||||
CONNECTOR_DVI_I,
|
||||
CONNECTOR_DVI_D
|
||||
};
|
||||
|
||||
static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
|
||||
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
|
||||
@ -89,6 +135,9 @@ static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
|
||||
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
|
||||
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
|
||||
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
|
||||
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
|
||||
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
|
||||
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
|
||||
{ 0, }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
|
||||
@ -177,7 +226,9 @@ struct radeon_regs {
|
||||
int bpp;
|
||||
u32 crtc_gen_cntl;
|
||||
u32 crtc_ext_cntl;
|
||||
#if defined(__BIG_ENDIAN)
|
||||
u32 surface_cntl;
|
||||
#endif
|
||||
u32 dac_cntl;
|
||||
u32 dda_config;
|
||||
u32 dda_on_off;
|
||||
@ -195,6 +246,12 @@ struct radeonfb_info {
|
||||
char name[14];
|
||||
char ram_type[12];
|
||||
|
||||
int hasCRTC2;
|
||||
int crtDispType;
|
||||
int dviDispType;
|
||||
int hasTVout;
|
||||
int isM7;
|
||||
|
||||
u32 mmio_base_phys;
|
||||
u32 fb_base_phys;
|
||||
|
||||
@ -592,9 +649,24 @@ module_exit(radeonfb_exit);
|
||||
#endif
|
||||
|
||||
|
||||
MODULE_AUTHOR("Ani Joshi");
|
||||
MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
|
||||
MODULE_AUTHOR("Ani Joshi. (Radeon VE extensions by Nick Kurshev)");
|
||||
MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset. Ver: "RADEON_VERSION);
|
||||
|
||||
static char * GET_MON_NAME(int type)
|
||||
{
|
||||
char *pret;
|
||||
switch(type)
|
||||
{
|
||||
case MT_NONE: pret = "no"; break;
|
||||
case MT_CRT: pret = "CRT"; break;
|
||||
case MT_DFP: pret = "DFP"; break;
|
||||
case MT_LCD: pret = "LCD"; break;
|
||||
case MT_CTV: pret = "CTV"; break;
|
||||
case MT_STV: pret = "STV"; break;
|
||||
default: pret = "Unknown";
|
||||
}
|
||||
return pret;
|
||||
}
|
||||
|
||||
|
||||
static int radeonfb_pci_register (struct pci_dev *pdev,
|
||||
@ -673,12 +745,34 @@ static int radeonfb_pci_register (struct pci_dev *pdev,
|
||||
strcpy(rinfo->name, "Radeon QG ");
|
||||
break;
|
||||
case PCI_DEVICE_ID_RADEON_QY:
|
||||
strcpy(rinfo->name, "Radeon VE QY");
|
||||
rinfo->hasCRTC2 = 1;
|
||||
strcpy(rinfo->name, "Radeon VE QY ");
|
||||
break;
|
||||
case PCI_DEVICE_ID_RADEON_QZ:
|
||||
strcpy(rinfo->name, "Radeon VE QZ");
|
||||
rinfo->hasCRTC2 = 1;
|
||||
strcpy(rinfo->name, "Radeon VE QZ ");
|
||||
break;
|
||||
case PCI_DEVICE_ID_RADEON_LY:
|
||||
rinfo->hasCRTC2 = 1;
|
||||
strcpy(rinfo->name, "Radeon M6 LY ");
|
||||
break;
|
||||
case PCI_DEVICE_ID_RADEON_LZ:
|
||||
rinfo->hasCRTC2 = 1;
|
||||
strcpy(rinfo->name, "Radeon M6 LZ ");
|
||||
break;
|
||||
case PCI_DEVICE_ID_RADEON_LW:
|
||||
/* Note: Only difference between VE,M6 and M7 is initialization CRTC2
|
||||
registers in dual monitor configuration!!! */
|
||||
rinfo->hasCRTC2 = 1;
|
||||
rinfo->isM7 = 1;
|
||||
strcpy(rinfo->name, "Radeon M7 LW ");
|
||||
break;
|
||||
default:
|
||||
release_mem_region (rinfo->mmio_base_phys,
|
||||
pci_resource_len(pdev, 2));
|
||||
release_mem_region (rinfo->fb_base_phys,
|
||||
pci_resource_len(pdev, 0));
|
||||
kfree (rinfo);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
@ -742,6 +836,61 @@ static int radeonfb_pci_register (struct pci_dev *pdev,
|
||||
|
||||
RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
|
||||
|
||||
/*****
|
||||
VE and M6 have both DVI and CRT ports (for M6 DVI port can be switch to
|
||||
DFP port). The DVI port can also be conneted to a CRT with an adapter.
|
||||
Here is the definition of ports for this driver---
|
||||
(1) If both port are connected, DVI port will be treated as the Primary
|
||||
port (uses CRTC1) and CRT port will be treated as the Secondary port
|
||||
(uses CRTC2)
|
||||
(2) If only one port is connected, it will treated as the Primary port
|
||||
(??? uses CRTC1 ???)
|
||||
*****/
|
||||
if(rinfo->hasCRTC2) {
|
||||
/* Using BIOS scratch registers works with for VE/M6,
|
||||
no such registers in regular RADEON!!!*/
|
||||
tmp = INREG(RADEON_BIOS_4_SCRATCH);
|
||||
/*check Primary (DVI/DFP port)*/
|
||||
if(tmp & 0x08) rinfo->dviDispType = MT_DFP;
|
||||
else if(tmp & 0x04) rinfo->dviDispType = MT_LCD;
|
||||
else if(tmp & 0x0200) rinfo->dviDispType = MT_CRT;
|
||||
else if(tmp & 0x10) rinfo->dviDispType = MT_CTV;
|
||||
else if(tmp & 0x20) rinfo->dviDispType = MT_STV;
|
||||
/*check Secondary (CRT port).*/
|
||||
if(tmp & 0x02) rinfo->crtDispType = MT_CRT;
|
||||
else if(tmp & 0x800) rinfo->crtDispType = MT_DFP;
|
||||
else if(tmp & 0x400) rinfo->crtDispType = MT_LCD;
|
||||
else if(tmp & 0x1000) rinfo->crtDispType = MT_CTV;
|
||||
else if(tmp & 0x2000) rinfo->crtDispType = MT_STV;
|
||||
if(rinfo->dviDispType == MT_NONE &&
|
||||
rinfo->crtDispType == MT_NONE) {
|
||||
printk("radeonfb: No monitor detected!!!\n");
|
||||
release_mem_region (rinfo->mmio_base_phys,
|
||||
pci_resource_len(pdev, 2));
|
||||
release_mem_region (rinfo->fb_base_phys,
|
||||
pci_resource_len(pdev, 0));
|
||||
kfree (rinfo);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
else {
|
||||
/*Regular Radeon ASIC, only one CRTC, but it could be
|
||||
used for DFP with a DVI output, like AIW board*/
|
||||
rinfo->dviDispType = MT_NONE;
|
||||
tmp = INREG(FP_GEN_CNTL);
|
||||
if(tmp & FP_EN_TMDS) rinfo->crtDispType = MT_DFP;
|
||||
else rinfo->crtDispType = MT_CRT;
|
||||
}
|
||||
|
||||
if(bios_seg) {
|
||||
/*
|
||||
FIXME!!! TVout support currently is incomplete
|
||||
On Radeon VE TVout is recognized as STV monitor on DVI port.
|
||||
*/
|
||||
char * bios_ptr = bios_seg + 0x48L;
|
||||
rinfo->hasTVout = readw(bios_ptr+0x32);
|
||||
}
|
||||
|
||||
rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
|
||||
rinfo->video_ram);
|
||||
if (!rinfo->fb_base) {
|
||||
@ -793,8 +942,15 @@ static int radeonfb_pci_register (struct pci_dev *pdev,
|
||||
radeon_engine_init (rinfo);
|
||||
}
|
||||
|
||||
printk ("radeonfb: ATI %s %d MB\n", rinfo->name,
|
||||
printk ("radeonfb: ATI %s %s %d MB\n",rinfo->name,rinfo->ram_type,
|
||||
(rinfo->video_ram/(1024*1024)));
|
||||
if(rinfo->hasCRTC2) {
|
||||
printk("radeonfb: DVI port has %s monitor connected\n",GET_MON_NAME(rinfo->dviDispType));
|
||||
printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
||||
}
|
||||
else
|
||||
printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
||||
printk("radeonfb: This card has %sTVout\n",rinfo->hasTVout ? "" : "no ");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -833,9 +989,12 @@ static char *radeon_find_rom(struct radeonfb_info *rinfo)
|
||||
char *rom_base;
|
||||
char *rom;
|
||||
int stage;
|
||||
int i;
|
||||
int i,j;
|
||||
char aty_rom_sig[] = "761295520";
|
||||
char radeon_sig[] = "RG6";
|
||||
char *radeon_sig[] = {
|
||||
"RG6",
|
||||
"RADEON"
|
||||
};
|
||||
|
||||
for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
|
||||
stage = 1;
|
||||
@ -867,10 +1026,14 @@ static char *radeon_find_rom(struct radeonfb_info *rinfo)
|
||||
rom = rom_base;
|
||||
|
||||
for (i = 0; (i < 512) && (stage != 4); i++) {
|
||||
if (radeon_sig[0] == *rom)
|
||||
if (strncmp(radeon_sig, rom,
|
||||
strlen(radeon_sig)) == 0)
|
||||
stage = 4;
|
||||
for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
|
||||
if (radeon_sig[j][0] == *rom)
|
||||
if (strncmp(radeon_sig[j], rom,
|
||||
strlen(radeon_sig[j])) == 0) {
|
||||
stage = 4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
rom++;
|
||||
}
|
||||
if (stage != 4) {
|
||||
@ -1533,8 +1696,9 @@ static void radeonfb_blank (int blank, struct fb_info *info)
|
||||
CRTC_HSYNC_DIS);
|
||||
break;
|
||||
}
|
||||
|
||||
OUTREG(CRTC_EXT_CNTL, val);
|
||||
if(blank == VESA_NO_BLANKING && rinfo->hasCRTC2)
|
||||
OUTREGP(CRTC_EXT_CNTL,CRTC_CRT_ON, val);
|
||||
else OUTREG(CRTC_EXT_CNTL, val);
|
||||
}
|
||||
|
||||
|
||||
@ -1769,9 +1933,10 @@ static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
||||
|
||||
newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
|
||||
(format << 8);
|
||||
|
||||
newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
|
||||
|
||||
if(rinfo->hasCRTC2)
|
||||
/* HACKED: !!! Enable CRT port here !!! */
|
||||
newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
|
||||
else newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
|
||||
newmode.dac_cntl = INREG(DAC_CNTL) | DAC_MASK_ALL | DAC_VGA_ADR_EN |
|
||||
DAC_8BIT_EN;
|
||||
|
||||
@ -1789,8 +1954,8 @@ static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
||||
|
||||
newmode.crtc_pitch = (mode->xres >> 3);
|
||||
|
||||
newmode.surface_cntl = SURF_TRANSLATION_DIS;
|
||||
#if defined(__BIG_ENDIAN)
|
||||
newmode.surface_cntl = SURF_TRANSLATION_DIS;
|
||||
switch (mode->bits_per_pixel) {
|
||||
case 16:
|
||||
newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
|
||||
@ -1890,11 +2055,23 @@ static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
||||
|
||||
/* do it! */
|
||||
radeon_write_mode (rinfo, &newmode);
|
||||
/* XXX absurd hack for X to restore console on VE */
|
||||
if(rinfo->hasCRTC2 && rinfo->crtDispType == MT_CRT &&
|
||||
(rinfo->dviDispType == MT_NONE || rinfo->dviDispType == MT_STV)) {
|
||||
OUTREG(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl);
|
||||
OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/*****
|
||||
When changing mode with Dual-head card (VE/M6), care must
|
||||
be taken for the special order in setting registers. CRTC2 has
|
||||
to be set before changing CRTC_EXT register.
|
||||
Otherwise we may get a blank screen.
|
||||
*****/
|
||||
|
||||
static void radeon_write_mode (struct radeonfb_info *rinfo,
|
||||
struct radeon_regs *mode)
|
||||
@ -1918,7 +2095,11 @@ static void radeon_write_mode (struct radeonfb_info *rinfo,
|
||||
OUTREG(CRTC_OFFSET, 0);
|
||||
OUTREG(CRTC_OFFSET_CNTL, 0);
|
||||
OUTREG(CRTC_PITCH, mode->crtc_pitch);
|
||||
#if defined(__BIG_ENDIAN)
|
||||
/* XXX this code makes degradation of mplayer quality on Radeon VE */
|
||||
OUTREG(SURFACE_CNTL, mode->surface_cntl);
|
||||
#endif
|
||||
/* Here we should restore FP registers for LCD & DFP monitors */
|
||||
|
||||
while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
|
||||
PPLL_DIV_SEL_MASK) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user