mirror of
https://github.com/mpv-player/mpv
synced 2025-01-24 19:37:30 +01:00
Works with YUY2 fourcc
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@4722 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick
parent
e7e053459c
commit
2cfd635666
@ -3,8 +3,7 @@
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Copyrights 2002 Nick Kurshev. This file is based on sources from
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GATOS (gatos.sf.net) and X11 (www.xfree86.org)
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Licence: GPL
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WARNING: THIS DRIVER WAS UNFINISHED! PLEASE DON'T TRY TO USE THAT!!!
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IT'S JUST SCRATCH FOR VOLUNTEERS!!!
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WARNING: THIS DRIVER IS IN BETTA STAGE AND DOESN'T WORK WITH PLANAR FOURCCS!
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*/
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#include <errno.h>
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#include <stdio.h>
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@ -26,22 +25,104 @@
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static void *mach64_mmio_base = 0;
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static void *mach64_mem_base = 0;
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static int32_t overlay_offset = 0;
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static int32_t mach64_overlay_offset = 0;
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static uint32_t mach64_ram_size = 0;
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pciinfo_t pci_info;
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static int probed = 0;
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static int __verbose = 0;
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typedef struct bes_registers_s
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{
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/* base address of yuv framebuffer */
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uint32_t yuv_base;
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uint32_t fourcc;
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/* YUV BES registers */
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uint32_t reg_load_cntl;
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uint32_t scale_inc;
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uint32_t y_x_start;
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uint32_t y_x_end;
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uint32_t vid_buf_pitch;
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uint32_t height_width;
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uint32_t vid_buf0_base_adrs;
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uint32_t vid_buf1_base_adrs;
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uint32_t vid_buf2_base_adrs;
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uint32_t vid_buf3_base_adrs;
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uint32_t vid_buf4_base_adrs;
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uint32_t vid_buf5_base_adrs;
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uint32_t scale_cntl;
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uint32_t exclusive_horz;
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uint32_t auto_flip_cntl;
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uint32_t filter_cntl;
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uint32_t key_cntl;
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uint32_t test;
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/* Configurable stuff */
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int double_buff;
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int brightness;
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int saturation;
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int ckey_on;
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uint32_t graphics_key_clr;
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uint32_t graphics_key_msk;
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int deinterlace_on;
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uint32_t deinterlace_pattern;
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} bes_registers_t;
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static bes_registers_t besr;
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typedef struct video_registers_s
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{
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const char * sname;
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uint32_t name;
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uint32_t value;
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}video_registers_t;
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static bes_registers_t besr;
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#define DECLARE_VREG(name) { #name, name, 0 }
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static video_registers_t vregs[] =
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{
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DECLARE_VREG(OVERLAY_SCALE_INC),
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DECLARE_VREG(OVERLAY_Y_X_START),
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DECLARE_VREG(OVERLAY_Y_X_END),
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DECLARE_VREG(OVERLAY_SCALE_CNTL),
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DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ),
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DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT),
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DECLARE_VREG(OVERLAY_TEST),
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DECLARE_VREG(SCALER_BUF_PITCH),
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DECLARE_VREG(SCALER_HEIGHT_WIDTH),
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DECLARE_VREG(SCALER_BUF0_OFFSET),
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DECLARE_VREG(SCALER_BUF0_OFFSET_U),
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DECLARE_VREG(SCALER_BUF0_OFFSET_V),
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DECLARE_VREG(SCALER_BUF1_OFFSET),
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DECLARE_VREG(SCALER_BUF1_OFFSET_U),
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DECLARE_VREG(SCALER_BUF1_OFFSET_V),
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DECLARE_VREG(SCALER_H_COEFF0),
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DECLARE_VREG(SCALER_H_COEFF1),
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DECLARE_VREG(SCALER_H_COEFF2),
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DECLARE_VREG(SCALER_H_COEFF3),
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DECLARE_VREG(SCALER_H_COEFF4),
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DECLARE_VREG(SCALER_COLOUR_CNTL),
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DECLARE_VREG(SCALER_THRESHOLD),
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DECLARE_VREG(VIDEO_FORMAT),
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DECLARE_VREG(VIDEO_CONFIG),
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DECLARE_VREG(VIDEO_SYNC_TEST),
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DECLARE_VREG(VIDEO_SYNC_TEST_B)
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};
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/* VIDIX exports */
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/* MMIO space*/
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#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
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#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
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#define INREG8(addr) GETREG(uint8_t,(uint32_t)(mach64_mmio_base),(addr^0x100)<<2)
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#define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(mach64_mmio_base),(addr^0x100)<<2,val)
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#define INREG(addr) GETREG(uint32_t,(uint32_t)(mach64_mmio_base),(addr^0x100)<<2)
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#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(mach64_mmio_base),(addr^0x100)<<2,val)
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#define INREG8(addr) GETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2)
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#define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val)
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#define INREG(addr) GETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2)
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#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val)
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#define OUTREGP(addr,val,mask) \
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do { \
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@ -53,12 +134,24 @@ static int __verbose = 0;
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static __inline__ uint32_t INPLL(uint32_t addr)
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{
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OUTREG8(0x491, (addr & 0x0000001f));
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return (INREG(0x492));
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uint32_t res;
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/* write addr byte */
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OUTREG8(CLOCK_CNTL + 1, (addr << 2));
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/* read the register value */
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res = INREG(CLOCK_CNTL + 2);
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return res;
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}
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static __inline__ void OUTPLL(uint32_t addr,uint32_t val)
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{
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/* write addr byte */
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OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN);
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/* write the register value */
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OUTREG(CLOCK_CNTL + 2, val);
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OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN);
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}
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#define OUTPLL(addr,val) OUTREG8(0x491, (addr & 0x0000001f) | 0x00000080); \
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OUTREG(0x492, val)
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#define OUTPLLP(addr,val,mask) \
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do { \
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unsigned int _tmp = INPLL(addr); \
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@ -67,6 +160,17 @@ static __inline__ uint32_t INPLL(uint32_t addr)
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OUTPLL(addr, _tmp); \
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} while (0)
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static void mach64_fifo_wait(unsigned n)
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{
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while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n)));
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}
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static void mach64_wait_for_idle( void )
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{
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mach64_fifo_wait(16);
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while ((INREG(GUI_STAT) & 1)!= 0);
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}
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static vidix_capability_t mach64_cap =
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{
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"BES driver for Mach64/3DRage cards",
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@ -84,6 +188,75 @@ static vidix_capability_t mach64_cap =
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{ 0, 0, 0, 0 }
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};
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static uint32_t mach64_vid_get_dbpp( void )
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{
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uint32_t dbpp,retval;
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dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7;
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switch(dbpp)
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{
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case 1: retval = 4; break;
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case 2: retval = 8; break;
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case 3: retval = 15; break;
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case 4: retval = 16; break;
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case 5: retval = 24; break;
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default: retval=32; break;
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}
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return retval;
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}
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static int mach64_is_dbl_scan( void )
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{
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return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN;
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}
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static int mach64_is_interlace( void )
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{
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return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN;
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}
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static uint32_t mach64_get_xres( void )
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{
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/* FIXME: currently we extract that from CRTC!!!*/
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uint32_t xres,h_total;
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h_total = INREG(CRTC_H_TOTAL_DISP);
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xres = (h_total >> 16) & 0xffff;
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return (xres + 1)*8;
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}
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static uint32_t mach64_get_yres( void )
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{
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/* FIXME: currently we extract that from CRTC!!!*/
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uint32_t yres,v_total;
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v_total = INREG(CRTC_V_TOTAL_DISP);
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yres = (v_total >> 16) & 0xffff;
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return yres + 1;
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}
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static void mach64_vid_make_default()
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{
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mach64_fifo_wait(2);
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OUTREG(SCALER_COLOUR_CNTL,0x0010103f);
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}
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static void mach64_vid_dump_regs( void )
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{
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size_t i;
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printf("[mach64] *** Begin of DRIVER variables dump ***\n");
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printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base);
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printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base);
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printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset);
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printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size);
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printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp());
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printf("[mach64] *** Begin of OV0 registers dump ***\n");
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for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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{
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mach64_wait_for_idle();
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printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name));
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}
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printf("[mach64] *** End of OV0 registers dump ***\n");
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}
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unsigned int vixGetVersion(void)
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{
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return(VIDIX_VERSION);
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@ -187,6 +360,17 @@ int vixProbe(int verbose,int force)
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return err;
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}
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static void reset_regs( void )
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{
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size_t i;
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for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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{
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mach64_fifo_wait(2);
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OUTREG(vregs[i].name,-1);
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}
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}
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int vixInit(void)
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{
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int err;
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@ -195,7 +379,8 @@ int vixInit(void)
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printf("[mach64] Driver was not probed but is being initializing\n");
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return EINTR;
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}
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if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4096))==(void *)-1) return ENOMEM;
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if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM;
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mach64_wait_for_idle();
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mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB;
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if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512;
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else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024;
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@ -203,17 +388,19 @@ int vixInit(void)
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mach64_ram_size *= 0x400; /* KB -> bytes */
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if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM;
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// memset(&besr,0,sizeof(bes_registers_t));
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// mach64_vid_make_default();
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mach64_vid_make_default();
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printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000);
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err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB);
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if(!err) printf("[mach64] Set write-combining type of video memory\n");
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reset_regs();
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mach64_vid_dump_regs();
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return 0;
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}
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void vixDestroy(void)
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{
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unmap_phys_mem(mach64_mem_base,mach64_ram_size);
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unmap_phys_mem(mach64_mmio_base,0x4096);
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unmap_phys_mem(mach64_mmio_base,0x4000);
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}
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int vixGetCapability(vidix_capability_t *to)
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@ -222,30 +409,371 @@ int vixGetCapability(vidix_capability_t *to)
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return 0;
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}
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static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch)
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{
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unsigned pitch,spy,spv,spu;
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spy = spv = spu = 0;
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switch(spitch->y)
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{
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case 16:
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case 32:
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case 64:
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case 128:
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case 256: spy = spitch->y; break;
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default: break;
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}
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switch(spitch->u)
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{
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case 16:
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case 32:
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case 64:
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case 128:
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case 256: spu = spitch->u; break;
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default: break;
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}
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switch(spitch->v)
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{
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case 16:
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case 32:
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case 64:
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case 128:
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case 256: spv = spitch->v; break;
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default: break;
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}
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switch(fourcc)
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{
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/* 4:2:0 */
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case IMGFMT_IYUV:
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case IMGFMT_YV12:
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case IMGFMT_I420:
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if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy;
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else pitch = 32;
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break;
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default:
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if(spy > 16) pitch = spy;
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else pitch = 32;
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break;
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}
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return pitch;
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}
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static void mach64_compute_framesize(vidix_playback_t *info)
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{
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unsigned pitch,awidth;
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pitch = mach64_query_pitch(info->fourcc,&info->src.pitch);
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switch(info->fourcc)
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{
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case IMGFMT_I420:
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case IMGFMT_YV12:
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case IMGFMT_IYUV:
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awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
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info->frame_size = awidth*(info->src.h+info->src.h/2);
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break;
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case IMGFMT_RGB32:
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case IMGFMT_BGR32:
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awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1);
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info->frame_size = (awidth*info->src.h);
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break;
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/* YUY2 YVYU, RGB15, RGB16 */
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default:
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awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1);
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info->frame_size = (awidth*info->src.h);
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break;
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}
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}
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static void mach64_vid_stop_video( void )
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{
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mach64_fifo_wait(14);
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OUTREG(OVERLAY_SCALE_CNTL, 0x80000000);
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OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0);
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OUTREG(OVERLAY_EXCLUSIVE_VERT, 0);
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OUTREG(SCALER_H_COEFF0, 0x00002000);
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OUTREG(SCALER_H_COEFF1, 0x0D06200D);
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OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D);
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OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C);
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OUTREG(SCALER_H_COEFF4, 0x0C14140C);
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OUTREG(VIDEO_FORMAT, 0xB000B);
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OUTREG(OVERLAY_GRAPHICS_KEY_MSK, 0);
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OUTREG(OVERLAY_GRAPHICS_KEY_CLR, 0);
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OUTREG(OVERLAY_KEY_CNTL, 0x50);
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OUTREG(OVERLAY_TEST, 0x0);
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}
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static void mach64_vid_display_video( void )
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{
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uint32_t vf;
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mach64_fifo_wait(14);
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OUTREG(OVERLAY_Y_X_START, besr.y_x_start);
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OUTREG(OVERLAY_Y_X_END, besr.y_x_end);
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OUTREG(OVERLAY_SCALE_INC, besr.scale_inc);
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OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch);
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OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width);
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OUTREG(SCALER_BUF0_OFFSET, besr.vid_buf0_base_adrs);
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OUTREG(SCALER_BUF0_OFFSET_U, besr.vid_buf1_base_adrs);
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OUTREG(SCALER_BUF0_OFFSET_V, besr.vid_buf2_base_adrs);
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OUTREG(SCALER_BUF1_OFFSET, besr.vid_buf3_base_adrs);
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OUTREG(SCALER_BUF1_OFFSET_U, besr.vid_buf4_base_adrs);
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OUTREG(SCALER_BUF1_OFFSET_V, besr.vid_buf5_base_adrs);
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OUTREG(OVERLAY_SCALE_CNTL, 0x04000001 | (3<<30));
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mach64_wait_for_idle();
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vf = INREG(VIDEO_FORMAT);
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switch(besr.fourcc)
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{
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/* 4:2:0 */
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case IMGFMT_IYUV:
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case IMGFMT_I420:
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case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, (vf & ~0xF000) | 0xA000); break;
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/* 4:2:2 */
|
||||
case IMGFMT_YVYU:
|
||||
case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, (vf & ~0xF000) | 0xB000); break;
|
||||
case IMGFMT_YUY2:
|
||||
default: OUTREG(VIDEO_FORMAT, (vf & ~0xF000) | 0xC000); break;
|
||||
}
|
||||
// OUTPLL(PLL_SCALER_LOCK_EN, 0);
|
||||
if(__verbose > 1) mach64_vid_dump_regs();
|
||||
}
|
||||
|
||||
static int mach64_vid_init_video( vidix_playback_t *config )
|
||||
{
|
||||
uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp;
|
||||
int is_420,best_pitch,mpitch;
|
||||
mach64_vid_stop_video();
|
||||
left = config->src.x << 16;
|
||||
top = config->src.y << 16;
|
||||
src_h = config->src.h;
|
||||
src_w = config->src.w;
|
||||
is_420 = 0;
|
||||
if(config->fourcc == IMGFMT_YV12 ||
|
||||
config->fourcc == IMGFMT_I420 ||
|
||||
config->fourcc == IMGFMT_IYUV) is_420 = 1;
|
||||
best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch);
|
||||
mpitch = best_pitch-1;
|
||||
switch(config->fourcc)
|
||||
{
|
||||
/* 4:2:0 */
|
||||
case IMGFMT_IYUV:
|
||||
case IMGFMT_YV12:
|
||||
case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch;
|
||||
config->dest.pitch.y =
|
||||
config->dest.pitch.u =
|
||||
config->dest.pitch.v = best_pitch;
|
||||
break;
|
||||
/* RGB 4:4:4:4 */
|
||||
case IMGFMT_RGB32:
|
||||
case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch;
|
||||
config->dest.pitch.y =
|
||||
config->dest.pitch.u =
|
||||
config->dest.pitch.v = best_pitch;
|
||||
break;
|
||||
/* 4:2:2 */
|
||||
default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */
|
||||
pitch = ((src_w*2) + mpitch) & ~mpitch;
|
||||
config->dest.pitch.y =
|
||||
config->dest.pitch.u =
|
||||
config->dest.pitch.v = best_pitch;
|
||||
break;
|
||||
}
|
||||
dest_w = config->dest.w;
|
||||
dest_h = config->dest.h;
|
||||
besr.fourcc = config->fourcc;
|
||||
ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4;
|
||||
v_inc = (src_h << (12
|
||||
+(mach64_is_interlace()?1:0)
|
||||
-(mach64_is_dbl_scan()?1:0)
|
||||
)) / dest_h;
|
||||
h_inc = (src_w << (12+ecp)) / dest_w;
|
||||
v_inc /= 2;
|
||||
/* keep everything in 16.16 */
|
||||
config->offsets[0] = 0;
|
||||
config->offsets[1] = config->frame_size;
|
||||
if(is_420)
|
||||
{
|
||||
uint32_t d1line,d2line,d3line;
|
||||
d1line = top*pitch;
|
||||
d2line = src_h*pitch+(d1line>>2);
|
||||
d3line = d2line+((src_h*pitch)>>2);
|
||||
d1line += (left >> 16) & ~15;
|
||||
d2line += (left >> 17) & ~15;
|
||||
d3line += (left >> 17) & ~15;
|
||||
config->offset.y = d1line & ~15;
|
||||
config->offset.v = d2line & ~15;
|
||||
config->offset.u = d3line & ~15;
|
||||
besr.vid_buf0_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.y)&~15);
|
||||
besr.vid_buf1_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.v)&~15);
|
||||
besr.vid_buf2_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.u)&~15);
|
||||
besr.vid_buf3_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.y)&~15);
|
||||
besr.vid_buf4_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.v)&~15);
|
||||
besr.vid_buf5_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.u)&~15);
|
||||
config->offset.y = ((besr.vid_buf0_base_adrs)&~15) - mach64_overlay_offset;
|
||||
config->offset.v = ((besr.vid_buf1_base_adrs)&~15) - mach64_overlay_offset;
|
||||
config->offset.u = ((besr.vid_buf2_base_adrs)&~15) - mach64_overlay_offset;
|
||||
if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
|
||||
{
|
||||
uint32_t tmp;
|
||||
tmp = config->offset.u;
|
||||
config->offset.u = config->offset.v;
|
||||
config->offset.v = tmp;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
besr.vid_buf0_base_adrs = mach64_overlay_offset;
|
||||
config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&~15;
|
||||
besr.vid_buf0_base_adrs += config->offset.y;
|
||||
besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs;
|
||||
besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs;
|
||||
besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size;
|
||||
besr.vid_buf4_base_adrs = besr.vid_buf0_base_adrs+config->frame_size;
|
||||
besr.vid_buf5_base_adrs = besr.vid_buf0_base_adrs+config->frame_size;
|
||||
}
|
||||
|
||||
leftUV = (left >> 17) & 15;
|
||||
left = (left >> 16) & 15;
|
||||
besr.scale_inc = ( h_inc << 16 ) | v_inc;
|
||||
besr.y_x_start = config->dest.y | (config->dest.x << 16);
|
||||
besr.y_x_end = (config->dest.y + dest_h) | ((config->dest.x + dest_w) << 16);
|
||||
besr.height_width = ((src_w - left)<<16) | (src_h - top);
|
||||
besr.vid_buf_pitch = pitch;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
uint32_t supported_fourcc[] =
|
||||
{
|
||||
IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV,
|
||||
IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU
|
||||
};
|
||||
|
||||
__inline__ static int is_supported_fourcc(uint32_t fourcc)
|
||||
{
|
||||
unsigned i;
|
||||
for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++)
|
||||
{
|
||||
if(fourcc==supported_fourcc[i]) return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vixQueryFourcc(vidix_fourcc_t *to)
|
||||
{
|
||||
UNUSED(to);
|
||||
if(is_supported_fourcc(to->fourcc))
|
||||
{
|
||||
to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
|
||||
VID_DEPTH_4BPP | VID_DEPTH_8BPP |
|
||||
VID_DEPTH_12BPP| VID_DEPTH_15BPP|
|
||||
VID_DEPTH_16BPP| VID_DEPTH_24BPP|
|
||||
VID_DEPTH_32BPP;
|
||||
to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK;
|
||||
return 0;
|
||||
}
|
||||
else to->depth = to->flags = 0;
|
||||
return ENOSYS;
|
||||
}
|
||||
|
||||
int vixConfigPlayback(vidix_playback_t *info)
|
||||
{
|
||||
UNUSED(info);
|
||||
return ENOSYS;
|
||||
if(!is_supported_fourcc(info->fourcc)) return ENOSYS;
|
||||
if(info->num_frames>2) info->num_frames=2;
|
||||
if(info->num_frames==1) besr.double_buff=0;
|
||||
else besr.double_buff=1;
|
||||
mach64_compute_framesize(info);
|
||||
mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames;
|
||||
mach64_overlay_offset &= 0xffff0000;
|
||||
if(mach64_overlay_offset < 0) return EINVAL;
|
||||
info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset;
|
||||
mach64_vid_init_video(info);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vixPlaybackOn(void)
|
||||
{
|
||||
return ENOSYS;
|
||||
mach64_vid_display_video();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vixPlaybackOff(void)
|
||||
{
|
||||
return ENOSYS;
|
||||
mach64_vid_stop_video();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mach64_wait_vsync( void )
|
||||
{
|
||||
#warning MACH64 VSYNC WAS NOT IMPLEMENTED!!!
|
||||
}
|
||||
|
||||
int vixPlaybackFrameSelect(unsigned int frame)
|
||||
{
|
||||
UNUSED(frame);
|
||||
return ENOSYS;
|
||||
uint32_t off[6];
|
||||
/*
|
||||
buf3-5 always should point onto second buffer for better
|
||||
deinterlacing and TV-in
|
||||
*/
|
||||
if(!besr.double_buff) return 0;
|
||||
if((frame%2))
|
||||
{
|
||||
off[0] = besr.vid_buf3_base_adrs;
|
||||
off[1] = besr.vid_buf4_base_adrs;
|
||||
off[2] = besr.vid_buf5_base_adrs;
|
||||
off[3] = besr.vid_buf0_base_adrs;
|
||||
off[4] = besr.vid_buf1_base_adrs;
|
||||
off[5] = besr.vid_buf2_base_adrs;
|
||||
}
|
||||
else
|
||||
{
|
||||
off[0] = besr.vid_buf0_base_adrs;
|
||||
off[1] = besr.vid_buf1_base_adrs;
|
||||
off[2] = besr.vid_buf2_base_adrs;
|
||||
off[3] = besr.vid_buf3_base_adrs;
|
||||
off[4] = besr.vid_buf4_base_adrs;
|
||||
off[5] = besr.vid_buf5_base_adrs;
|
||||
}
|
||||
|
||||
mach64_wait_vsync();
|
||||
mach64_wait_for_idle();
|
||||
mach64_fifo_wait(7);
|
||||
OUTREG(SCALER_BUF0_OFFSET, off[0]);
|
||||
OUTREG(SCALER_BUF0_OFFSET_U, off[1]);
|
||||
OUTREG(SCALER_BUF0_OFFSET_V, off[2]);
|
||||
OUTREG(SCALER_BUF1_OFFSET, off[3]);
|
||||
OUTREG(SCALER_BUF1_OFFSET_U, off[4]);
|
||||
OUTREG(SCALER_BUF1_OFFSET_V, off[5]);
|
||||
if(__verbose > 1) mach64_vid_dump_regs();
|
||||
return 0;
|
||||
}
|
||||
|
||||
vidix_video_eq_t equal =
|
||||
{
|
||||
VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION
|
||||
,
|
||||
0, 0, 0, 0, 0, 0, 0, 0 };
|
||||
|
||||
int vixPlaybackGetEq( vidix_video_eq_t * eq)
|
||||
{
|
||||
memcpy(eq,&equal,sizeof(vidix_video_eq_t));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vixPlaybackSetEq( const vidix_video_eq_t * eq)
|
||||
{
|
||||
int br,sat;
|
||||
if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness;
|
||||
if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast;
|
||||
if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation;
|
||||
if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue;
|
||||
if(eq->cap & VEQ_CAP_RGB_INTENSITY)
|
||||
{
|
||||
equal.red_intensity = eq->red_intensity;
|
||||
equal.green_intensity = eq->green_intensity;
|
||||
equal.blue_intensity = eq->blue_intensity;
|
||||
}
|
||||
equal.flags = eq->flags;
|
||||
br = equal.brightness * 64 / 1000;
|
||||
if(br < -64) br = -64; if(br > 63) br = 63;
|
||||
sat = (equal.saturation + 1000) * 16 / 1000;
|
||||
if(sat < 0) sat = 0; if(sat > 31) sat = 31;
|
||||
OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16));
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user