mirror of
https://github.com/mpv-player/mpv
synced 2024-11-03 03:19:24 +01:00
304 lines
9.4 KiB
C
304 lines
9.4 KiB
C
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v 1.10 2001/11/04 22:17:48 alanh Exp $ */
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#ifndef _SAVAGE_REGS_H
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#define _SAVAGE_REGS_H
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/* These are here until xf86PciInfo.h is updated. */
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#ifndef PCI_CHIP_S3TWISTER_P
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#define PCI_CHIP_S3TWISTER_P 0x8d01
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#endif
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#ifndef PCI_CHIP_S3TWISTER_K
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#define PCI_CHIP_S3TWISTER_K 0x8d02
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#endif
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#ifndef PCI_CHIP_SUPSAV_MX128
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#define PCI_CHIP_SUPSAV_MX128 0x8c22
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#define PCI_CHIP_SUPSAV_MX64 0x8c24
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#define PCI_CHIP_SUPSAV_MX64C 0x8c26
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#define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
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#define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
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#define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
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#define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
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#define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
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#define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
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#endif
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#ifndef PCI_CHIP_PROSAVAGE_DDR
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#define PCI_CHIP_PROSAVAGE_DDR 0x8d03
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#define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
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#endif
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#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
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#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
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#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
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#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
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/* Chip tags. These are used to group the adapters into
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* related families.
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*/
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enum S3CHIPTAGS {
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S3_UNKNOWN = 0,
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S3_SAVAGE3D,
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S3_SAVAGE_MX,
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S3_SAVAGE4,
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S3_PROSAVAGE,
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S3_SUPERSAVAGE,
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S3_SAVAGE2000,
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S3_LAST
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};
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typedef struct {
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unsigned int mode, refresh;
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unsigned char SR08, SR0E, SR0F;
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unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR1B, SR29, SR30;
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unsigned char SR54[8];
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unsigned char Clock;
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unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
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unsigned char CR40, CR41, CR42, CR43, CR45;
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unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
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unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
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unsigned char CR86, CR88;
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unsigned char CR90, CR91, CRB0;
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unsigned int STREAMS[22]; /* yuck, streams regs */
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unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
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} SavageRegRec, *SavageRegPtr;
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#define BIOS_BSIZE 1024
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#define BIOS_BASE 0xc0000
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#define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
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#define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
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#define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
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#define SAVAGE_NEWMMIO_VGABASE 0x8000
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#define BASE_FREQ 14.31818
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#define FIFO_CONTROL_REG 0x8200
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#define MIU_CONTROL_REG 0x8204
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#define STREAMS_TIMEOUT_REG 0x8208
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#define MISC_TIMEOUT_REG 0x820c
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/* Stream Processor 1 */
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/* Primary Stream 1 Frame Buffer Address 0 */
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#define PRI_STREAM_FBUF_ADDR0 0x81c0
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/* Primary Stream 1 Frame Buffer Address 0 */
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#define PRI_STREAM_FBUF_ADDR1 0x81c4
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/* Primary Stream 1 Stride */
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#define PRI_STREAM_STRIDE 0x81c8
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/* Primary Stream 1 Frame Buffer Size */
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#define PRI_STREAM_BUFFERSIZE 0x8214
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/* Secondary stream 1 Color/Chroma Key Control */
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#define SEC_STREAM_CKEY_LOW 0x8184
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/* Secondary stream 1 Chroma Key Upper Bound */
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#define SEC_STREAM_CKEY_UPPER 0x8194
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/* Blend Control of Secondary Stream 1 & 2 */
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#define BLEND_CONTROL 0x8190
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/* Secondary Stream 1 Color conversion/Adjustment 1 */
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#define SEC_STREAM_COLOR_CONVERT1 0x8198
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/* Secondary Stream 1 Color conversion/Adjustment 2 */
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#define SEC_STREAM_COLOR_CONVERT2 0x819c
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/* Secondary Stream 1 Color conversion/Adjustment 3 */
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#define SEC_STREAM_COLOR_CONVERT3 0x81e4
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/* Secondary Stream 1 Horizontal Scaling */
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#define SEC_STREAM_HSCALING 0x81a0
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/* Secondary Stream 1 Frame Buffer Size */
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#define SEC_STREAM_BUFFERSIZE 0x81a8
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/* Secondary Stream 1 Horizontal Scaling Normalization (2K only) */
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#define SEC_STREAM_HSCALE_NORMALIZE 0x81ac
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/* Secondary Stream 1 Horizontal Scaling */
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#define SEC_STREAM_VSCALING 0x81e8
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/* Secondary Stream 1 Frame Buffer Address 0 */
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#define SEC_STREAM_FBUF_ADDR0 0x81d0
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/* Secondary Stream 1 Frame Buffer Address 1 */
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#define SEC_STREAM_FBUF_ADDR1 0x81d4
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/* Secondary Stream 1 Frame Buffer Address 2 */
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#define SEC_STREAM_FBUF_ADDR2 0x81ec
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/* Secondary Stream 1 Stride */
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#define SEC_STREAM_STRIDE 0x81d8
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/* Secondary Stream 1 Window Start Coordinates */
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#define SEC_STREAM_WINDOW_START 0x81f8
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/* Secondary Stream 1 Window Size */
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#define SEC_STREAM_WINDOW_SZ 0x81fc
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/* Secondary Streams Tile Offset */
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#define SEC_STREAM_TILE_OFF 0x821c
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/* Secondary Stream 1 Opaque Overlay Control */
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#define SEC_STREAM_OPAQUE_OVERLAY 0x81dc
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/* Stream Processor 2 */
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/* Primary Stream 2 Frame Buffer Address 0 */
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#define PRI_STREAM2_FBUF_ADDR0 0x81b0
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/* Primary Stream 2 Frame Buffer Address 1 */
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#define PRI_STREAM2_FBUF_ADDR1 0x81b4
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/* Primary Stream 2 Stride */
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#define PRI_STREAM2_STRIDE 0x81b8
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/* Primary Stream 2 Frame Buffer Size */
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#define PRI_STREAM2_BUFFERSIZE 0x8218
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/* Secondary Stream 2 Color/Chroma Key Control */
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#define SEC_STREAM2_CKEY_LOW 0x8188
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/* Secondary Stream 2 Chroma Key Upper Bound */
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#define SEC_STREAM2_CKEY_UPPER 0x818c
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/* Secondary Stream 2 Horizontal Scaling */
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#define SEC_STREAM2_HSCALING 0x81a4
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/* Secondary Stream 2 Horizontal Scaling */
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#define SEC_STREAM2_VSCALING 0x8204
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/* Secondary Stream 2 Frame Buffer Size */
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#define SEC_STREAM2_BUFFERSIZE 0x81ac
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/* Secondary Stream 2 Frame Buffer Address 0 */
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#define SEC_STREAM2_FBUF_ADDR0 0x81bc
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/* Secondary Stream 2 Frame Buffer Address 1 */
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#define SEC_STREAM2_FBUF_ADDR1 0x81e0
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/* Secondary Stream 2 Frame Buffer Address 2 */
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#define SEC_STREAM2_FBUF_ADDR2 0x8208
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/* Multiple Buffer/LPB and Secondary Stream 2 Stride */
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#define SEC_STREAM2_STRIDE_LPB 0x81cc
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/* Secondary Stream 2 Color conversion/Adjustment 1 */
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#define SEC_STREAM2_COLOR_CONVERT1 0x81f0
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/* Secondary Stream 2 Color conversion/Adjustment 2 */
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#define SEC_STREAM2_COLOR_CONVERT2 0x81f4
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/* Secondary Stream 2 Color conversion/Adjustment 3 */
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#define SEC_STREAM2_COLOR_CONVERT3 0x8200
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/* Secondary Stream 2 Window Start Coordinates */
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#define SEC_STREAM2_WINDOW_START 0x820c
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/* Secondary Stream 2 Window Size */
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#define SEC_STREAM2_WINDOW_SZ 0x8210
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/* Secondary Stream 2 Opaque Overlay Control */
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#define SEC_STREAM2_OPAQUE_OVERLAY 0x8180
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/* savage 2000 */
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#define SEC_STREAM_COLOR_CONVERT0_2000 0x8198
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#define SEC_STREAM_COLOR_CONVERT1_2000 0x819c
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#define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0
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#define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4
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#define SUBSYS_STAT_REG 0x8504
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#define SRC_BASE 0xa4d4
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#define DEST_BASE 0xa4d8
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#define CLIP_L_R 0xa4dc
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#define CLIP_T_B 0xa4e0
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#define DEST_SRC_STR 0xa4e4
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#define MONO_PAT_0 0xa4e8
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#define MONO_PAT_1 0xa4ec
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/* Constants for CR69. */
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#define CRT_ACTIVE 0x01
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#define LCD_ACTIVE 0x02
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#define TV_ACTIVE 0x04
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#define CRT_ATTACHED 0x10
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#define LCD_ATTACHED 0x20
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#define TV_ATTACHED 0x40
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/*
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* reads from SUBSYS_STAT
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*/
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#define STATUS_WORD0 (INREG(0x48C00))
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#define ALT_STATUS_WORD0 (INREG(0x48C60))
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#define MAXLOOP 0xffffff
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#define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG))
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#define MAXFIFO 0x7f00
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/*
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* NOTE: don't remove 'VGAIN8(vgaCRIndex);'.
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* If not present it will cause lockups on Savage4.
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* Ask S3, why.
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*/
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/*#define VerticalRetraceWait() \
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{ \
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VGAIN8(0x3d0+4); \
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VGAOUT8(0x3d0+4, 0x17); \
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if (VGAIN8(0x3d0+5) & 0x80) { \
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while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x08) ; \
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while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x00) ; \
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} \
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}
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*/
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#define VerticalRetraceWait() \
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do { \
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VGAIN8(0x3d4); \
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VGAOUT8(0x3d4, 0x17); \
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if (VGAIN8(0x3d5) & 0x80) { \
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int i = 0x10000; \
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while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \
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i = 0x10000; \
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while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \
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} \
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} while (0)
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#define I2C_REG 0xa0
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#define InI2CREG(a) \
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{ \
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VGAOUT8(0x3d0 + 4, I2C_REG); \
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a = VGAIN8(0x3d0 + 5); \
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}
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#define OutI2CREG(a) \
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{ \
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VGAOUT8(0x3d0 + 4, I2C_REG); \
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VGAOUT8(0x3d0 + 5, a); \
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}
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#define HZEXP_COMP_1 0x54
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#define HZEXP_BORDER 0x58
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#define HZEXP_FACTOR_IGA1 0x59
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#define VTEXP_COMP_1 0x56
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#define VTEXP_BORDER 0x5a
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#define VTEXP_FACTOR_IGA1 0x5b
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#define EC1_CENTER_ON 0x10
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#define EC1_EXPAND_ON 0x0c
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#define MODE_24 24
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#if (MODE_24 == 32)
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# define BYTES_PP24 4
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#else
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# define BYTES_PP24 3
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#endif
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#define OVERLAY_DEPTH 16
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#define STREAMS_MODE32 0x7
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#define STREAMS_MODE24 0x6
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#define STREAMS_MODE16 0x5 /* @@@ */
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#define DEPTH_BPP(depth) (depth == 24 ? (BYTES_PP24 << 3) : (depth + 7) & ~0x7)
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#define DEPTH_2ND(depth) (depth > 8 ? depth\
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: OVERLAY_DEPTH)
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#define SSTREAMS_MODE(bpp) (bpp > 16 ? (bpp > 24 ? STREAMS_MODE32 :\
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STREAMS_MODE24) : STREAMS_MODE16)
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#define HSCALING_Shift 0
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#define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift)
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#define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) \
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<< HSCALING_Shift) \
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& HSCALING_Mask)
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#define VSCALING_Shift 0
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#define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift)
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#define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) \
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<< VSCALING_Shift) \
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& VSCALING_Mask)
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#endif /* _SAVAGE_REGS_H */
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