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hashcat/OpenCL/m05600_a3.cl

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Initial commit
2015-12-04 15:47:52 +01:00
/**
Fixed all gpu code (see PR #179 for details)
2016-01-30 23:02:15 +01:00
* Authors.....: Jens Steube <jens.steube@gmail.com>
* Gabriele Gristina <matrix@hashcat.net>
*
Initial commit
2015-12-04 15:47:52 +01:00
* License.....: MIT
*/
#define _NETNTLMV2_
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
#define NEW_SIMD_CODE
Initial commit
2015-12-04 15:47:52 +01:00
#include "include/constants.h"
#include "include/kernel_vendor.h"
#define DGST_R0 0
#define DGST_R1 3
#define DGST_R2 2
#define DGST_R3 1
#include "include/kernel_functions.c"
Fix path to includes
2016-01-03 01:48:05 +01:00
#include "OpenCL/types_ocl.c"
#include "OpenCL/common.c"
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
#include "OpenCL/simd.c"
Initial commit
2015-12-04 15:47:52 +01:00
- Added inline declaration to functions from simd.c, common.c, rp.c and types_ocl.c to increase performance - Dropped static declaration from functions in all kernel to achieve OpenCL 1.1 compatibility - Added -cl-std=CL1.1 to all kernel build options - Created environment variable to inform NVidia OpenCL runtime to not create its own kernel cache - Created environment variable to inform pocl OpenCL runtime to not create its own kernel cache
2016-05-01 23:15:26 +02:00
void md4_transform (const u32x w0[4], const u32x w1[4], const u32x w2[4], const u32x w3[4], u32x digest[4])
Initial commit
2015-12-04 15:47:52 +01:00
{
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
u32x a = digest[0];
u32x b = digest[1];
u32x c = digest[2];
u32x d = digest[3];
u32x w0_t = w0[0];
u32x w1_t = w0[1];
u32x w2_t = w0[2];
u32x w3_t = w0[3];
u32x w4_t = w1[0];
u32x w5_t = w1[1];
u32x w6_t = w1[2];
u32x w7_t = w1[3];
u32x w8_t = w2[0];
u32x w9_t = w2[1];
u32x wa_t = w2[2];
u32x wb_t = w2[3];
u32x wc_t = w3[0];
u32x wd_t = w3[1];
u32x we_t = w3[2];
u32x wf_t = w3[3];
Initial commit
2015-12-04 15:47:52 +01:00
MD4_STEP (MD4_Fo, a, b, c, d, w0_t, MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w1_t, MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w2_t, MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w3_t, MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w4_t, MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w5_t, MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, w6_t, MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, w7_t, MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, w8_t, MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, w9_t, MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, wa_t, MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, wb_t, MD4C00, MD4S03);
MD4_STEP (MD4_Fo, a, b, c, d, wc_t, MD4C00, MD4S00);
MD4_STEP (MD4_Fo, d, a, b, c, wd_t, MD4C00, MD4S01);
MD4_STEP (MD4_Fo, c, d, a, b, we_t, MD4C00, MD4S02);
MD4_STEP (MD4_Fo, b, c, d, a, wf_t, MD4C00, MD4S03);
MD4_STEP (MD4_Go, a, b, c, d, w0_t, MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w4_t, MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w8_t, MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, wc_t, MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w1_t, MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w5_t, MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, w9_t, MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, wd_t, MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w2_t, MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w6_t, MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, wa_t, MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, we_t, MD4C01, MD4S13);
MD4_STEP (MD4_Go, a, b, c, d, w3_t, MD4C01, MD4S10);
MD4_STEP (MD4_Go, d, a, b, c, w7_t, MD4C01, MD4S11);
MD4_STEP (MD4_Go, c, d, a, b, wb_t, MD4C01, MD4S12);
MD4_STEP (MD4_Go, b, c, d, a, wf_t, MD4C01, MD4S13);
MD4_STEP (MD4_H , a, b, c, d, w0_t, MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w8_t, MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w4_t, MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, wc_t, MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w2_t, MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, wa_t, MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w6_t, MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, we_t, MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w1_t, MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, w9_t, MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w5_t, MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, wd_t, MD4C02, MD4S23);
MD4_STEP (MD4_H , a, b, c, d, w3_t, MD4C02, MD4S20);
MD4_STEP (MD4_H , d, a, b, c, wb_t, MD4C02, MD4S21);
MD4_STEP (MD4_H , c, d, a, b, w7_t, MD4C02, MD4S22);
MD4_STEP (MD4_H , b, c, d, a, wf_t, MD4C02, MD4S23);
digest[0] += a;
digest[1] += b;
digest[2] += c;
digest[3] += d;
}
- Added inline declaration to functions from simd.c, common.c, rp.c and types_ocl.c to increase performance - Dropped static declaration from functions in all kernel to achieve OpenCL 1.1 compatibility - Added -cl-std=CL1.1 to all kernel build options - Created environment variable to inform NVidia OpenCL runtime to not create its own kernel cache - Created environment variable to inform pocl OpenCL runtime to not create its own kernel cache
2016-05-01 23:15:26 +02:00
void md5_transform (const u32x w0[4], const u32x w1[4], const u32x w2[4], const u32x w3[4], u32x digest[4])
Initial commit
2015-12-04 15:47:52 +01:00
{
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
u32x a = digest[0];
u32x b = digest[1];
u32x c = digest[2];
u32x d = digest[3];
u32x w0_t = w0[0];
u32x w1_t = w0[1];
u32x w2_t = w0[2];
u32x w3_t = w0[3];
u32x w4_t = w1[0];
u32x w5_t = w1[1];
u32x w6_t = w1[2];
u32x w7_t = w1[3];
u32x w8_t = w2[0];
u32x w9_t = w2[1];
u32x wa_t = w2[2];
u32x wb_t = w2[3];
u32x wc_t = w3[0];
u32x wd_t = w3[1];
u32x we_t = w3[2];
u32x wf_t = w3[3];
Initial commit
2015-12-04 15:47:52 +01:00
MD5_STEP (MD5_Fo, a, b, c, d, w0_t, MD5C00, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, w1_t, MD5C01, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, w2_t, MD5C02, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, w3_t, MD5C03, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, w4_t, MD5C04, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, w5_t, MD5C05, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, w6_t, MD5C06, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, w7_t, MD5C07, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, w8_t, MD5C08, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, w9_t, MD5C09, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, wa_t, MD5C0a, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, wb_t, MD5C0b, MD5S03);
MD5_STEP (MD5_Fo, a, b, c, d, wc_t, MD5C0c, MD5S00);
MD5_STEP (MD5_Fo, d, a, b, c, wd_t, MD5C0d, MD5S01);
MD5_STEP (MD5_Fo, c, d, a, b, we_t, MD5C0e, MD5S02);
MD5_STEP (MD5_Fo, b, c, d, a, wf_t, MD5C0f, MD5S03);
MD5_STEP (MD5_Go, a, b, c, d, w1_t, MD5C10, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, w6_t, MD5C11, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, wb_t, MD5C12, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, w0_t, MD5C13, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, w5_t, MD5C14, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, wa_t, MD5C15, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, wf_t, MD5C16, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, w4_t, MD5C17, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, w9_t, MD5C18, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, we_t, MD5C19, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, w3_t, MD5C1a, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, w8_t, MD5C1b, MD5S13);
MD5_STEP (MD5_Go, a, b, c, d, wd_t, MD5C1c, MD5S10);
MD5_STEP (MD5_Go, d, a, b, c, w2_t, MD5C1d, MD5S11);
MD5_STEP (MD5_Go, c, d, a, b, w7_t, MD5C1e, MD5S12);
MD5_STEP (MD5_Go, b, c, d, a, wc_t, MD5C1f, MD5S13);
MD5_STEP (MD5_H , a, b, c, d, w5_t, MD5C20, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, w8_t, MD5C21, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, wb_t, MD5C22, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, we_t, MD5C23, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, w1_t, MD5C24, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, w4_t, MD5C25, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, w7_t, MD5C26, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, wa_t, MD5C27, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, wd_t, MD5C28, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, w0_t, MD5C29, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, w3_t, MD5C2a, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, w6_t, MD5C2b, MD5S23);
MD5_STEP (MD5_H , a, b, c, d, w9_t, MD5C2c, MD5S20);
MD5_STEP (MD5_H , d, a, b, c, wc_t, MD5C2d, MD5S21);
MD5_STEP (MD5_H , c, d, a, b, wf_t, MD5C2e, MD5S22);
MD5_STEP (MD5_H , b, c, d, a, w2_t, MD5C2f, MD5S23);
MD5_STEP (MD5_I , a, b, c, d, w0_t, MD5C30, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, w7_t, MD5C31, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, we_t, MD5C32, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, w5_t, MD5C33, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, wc_t, MD5C34, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, w3_t, MD5C35, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, wa_t, MD5C36, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, w1_t, MD5C37, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, w8_t, MD5C38, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, wf_t, MD5C39, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, w6_t, MD5C3a, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, wd_t, MD5C3b, MD5S33);
MD5_STEP (MD5_I , a, b, c, d, w4_t, MD5C3c, MD5S30);
MD5_STEP (MD5_I , d, a, b, c, wb_t, MD5C3d, MD5S31);
MD5_STEP (MD5_I , c, d, a, b, w2_t, MD5C3e, MD5S32);
MD5_STEP (MD5_I , b, c, d, a, w9_t, MD5C3f, MD5S33);
digest[0] += a;
digest[1] += b;
digest[2] += c;
digest[3] += d;
}
- Added inline declaration to functions from simd.c, common.c, rp.c and types_ocl.c to increase performance - Dropped static declaration from functions in all kernel to achieve OpenCL 1.1 compatibility - Added -cl-std=CL1.1 to all kernel build options - Created environment variable to inform NVidia OpenCL runtime to not create its own kernel cache - Created environment variable to inform pocl OpenCL runtime to not create its own kernel cache
2016-05-01 23:15:26 +02:00
void hmac_md5_pad (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x ipad[4], u32x opad[4])
Initial commit
2015-12-04 15:47:52 +01:00
{
w0[0] = w0[0] ^ 0x36363636;
w0[1] = w0[1] ^ 0x36363636;
w0[2] = w0[2] ^ 0x36363636;
w0[3] = w0[3] ^ 0x36363636;
w1[0] = w1[0] ^ 0x36363636;
w1[1] = w1[1] ^ 0x36363636;
w1[2] = w1[2] ^ 0x36363636;
w1[3] = w1[3] ^ 0x36363636;
w2[0] = w2[0] ^ 0x36363636;
w2[1] = w2[1] ^ 0x36363636;
w2[2] = w2[2] ^ 0x36363636;
w2[3] = w2[3] ^ 0x36363636;
w3[0] = w3[0] ^ 0x36363636;
w3[1] = w3[1] ^ 0x36363636;
w3[2] = w3[2] ^ 0x36363636;
w3[3] = w3[3] ^ 0x36363636;
ipad[0] = MD5M_A;
ipad[1] = MD5M_B;
ipad[2] = MD5M_C;
ipad[3] = MD5M_D;
md5_transform (w0, w1, w2, w3, ipad);
w0[0] = w0[0] ^ 0x6a6a6a6a;
w0[1] = w0[1] ^ 0x6a6a6a6a;
w0[2] = w0[2] ^ 0x6a6a6a6a;
w0[3] = w0[3] ^ 0x6a6a6a6a;
w1[0] = w1[0] ^ 0x6a6a6a6a;
w1[1] = w1[1] ^ 0x6a6a6a6a;
w1[2] = w1[2] ^ 0x6a6a6a6a;
w1[3] = w1[3] ^ 0x6a6a6a6a;
w2[0] = w2[0] ^ 0x6a6a6a6a;
w2[1] = w2[1] ^ 0x6a6a6a6a;
w2[2] = w2[2] ^ 0x6a6a6a6a;
w2[3] = w2[3] ^ 0x6a6a6a6a;
w3[0] = w3[0] ^ 0x6a6a6a6a;
w3[1] = w3[1] ^ 0x6a6a6a6a;
w3[2] = w3[2] ^ 0x6a6a6a6a;
w3[3] = w3[3] ^ 0x6a6a6a6a;
opad[0] = MD5M_A;
opad[1] = MD5M_B;
opad[2] = MD5M_C;
opad[3] = MD5M_D;
md5_transform (w0, w1, w2, w3, opad);
}
- Added inline declaration to functions from simd.c, common.c, rp.c and types_ocl.c to increase performance - Dropped static declaration from functions in all kernel to achieve OpenCL 1.1 compatibility - Added -cl-std=CL1.1 to all kernel build options - Created environment variable to inform NVidia OpenCL runtime to not create its own kernel cache - Created environment variable to inform pocl OpenCL runtime to not create its own kernel cache
2016-05-01 23:15:26 +02:00
void hmac_md5_run (u32x w0[4], u32x w1[4], u32x w2[4], u32x w3[4], u32x ipad[4], u32x opad[4], u32x digest[4])
Initial commit
2015-12-04 15:47:52 +01:00
{
digest[0] = ipad[0];
digest[1] = ipad[1];
digest[2] = ipad[2];
digest[3] = ipad[3];
md5_transform (w0, w1, w2, w3, digest);
w0[0] = digest[0];
w0[1] = digest[1];
w0[2] = digest[2];
w0[3] = digest[3];
w1[0] = 0x80;
w1[1] = 0;
w1[2] = 0;
w1[3] = 0;
w2[0] = 0;
w2[1] = 0;
w2[2] = 0;
w2[3] = 0;
w3[0] = 0;
w3[1] = 0;
w3[2] = (64 + 16) * 8;
w3[3] = 0;
digest[0] = opad[0];
digest[1] = opad[1];
digest[2] = opad[2];
digest[3] = opad[3];
md5_transform (w0, w1, w2, w3, digest);
}
- Added inline declaration to functions from simd.c, common.c, rp.c and types_ocl.c to increase performance - Dropped static declaration from functions in all kernel to achieve OpenCL 1.1 compatibility - Added -cl-std=CL1.1 to all kernel build options - Created environment variable to inform NVidia OpenCL runtime to not create its own kernel cache - Created environment variable to inform pocl OpenCL runtime to not create its own kernel cache
2016-05-01 23:15:26 +02:00
void m05600m (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const u32 pw_len, __global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global netntlm_t *netntlm_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, __local u32 *s_userdomain_buf, __local u32 *s_chall_buf)
Initial commit
2015-12-04 15:47:52 +01:00
{
/**
* modifier
*/
const u32 gid = get_global_id (0);
const u32 lid = get_local_id (0);
/**
* prepare
*/
const u32 userdomain_len = netntlm_bufs[salt_pos].user_len
Cleanup -m 56xx kernels to latest standard
2016-04-12 21:21:35 +02:00
+ netntlm_bufs[salt_pos].domain_len;
Initial commit
2015-12-04 15:47:52 +01:00
const u32 chall_len = netntlm_bufs[salt_pos].srvchall_len
Cleanup -m 56xx kernels to latest standard
2016-04-12 21:21:35 +02:00
+ netntlm_bufs[salt_pos].clichall_len;
Initial commit
2015-12-04 15:47:52 +01:00
/**
* loop
*/
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w0l = w0[0];
Initial commit
2015-12-04 15:47:52 +01:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
for (u32 il_pos = 0; il_pos < il_cnt; il_pos += VECT_SIZE)
Initial commit
2015-12-04 15:47:52 +01:00
{
Prepare NEW_SIMD_MODE for -a 1 kernels
2016-02-20 16:13:06 +01:00
const u32x w0r = ix_create_bft (bfs_buf, il_pos);
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
const u32x w0lr = w0l | w0r;
Cleanup -m 56xx kernels to latest standard
2016-04-12 21:21:35 +02:00
/**
* pads
*/
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
u32x w0_t[4];
u32x w1_t[4];
u32x w2_t[4];
u32x w3_t[4];
Initial commit
2015-12-04 15:47:52 +01:00
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
w0_t[0] = w0lr;
w0_t[1] = w0[1];
w0_t[2] = w0[2];
w0_t[3] = w0[3];
w1_t[0] = w1[0];
w1_t[1] = w1[1];
w1_t[2] = w1[2];
w1_t[3] = w1[3];
w2_t[0] = w2[0];
w2_t[1] = w2[1];
w2_t[2] = w2[2];
w2_t[3] = w2[3];
w3_t[0] = w3[0];
w3_t[1] = w3[1];
w3_t[2] = w3[2];
w3_t[3] = w3[3];
u32x digest[4];
Initial commit
2015-12-04 15:47:52 +01:00
digest[0] = MD4M_A;
digest[1] = MD4M_B;
digest[2] = MD4M_C;
digest[3] = MD4M_D;
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
md4_transform (w0_t, w1_t, w2_t, w3_t, digest);
Initial commit
2015-12-04 15:47:52 +01:00
w0_t[0] = digest[0];
w0_t[1] = digest[1];
w0_t[2] = digest[2];
w0_t[3] = digest[3];
w1_t[0] = 0;
w1_t[1] = 0;
w1_t[2] = 0;
w1_t[3] = 0;
w2_t[0] = 0;
w2_t[1] = 0;
w2_t[2] = 0;
w2_t[3] = 0;
w3_t[0] = 0;
w3_t[1] = 0;
w3_t[2] = 0;
w3_t[3] = 0;
digest[0] = MD5M_A;
digest[1] = MD5M_B;
digest[2] = MD5M_C;
digest[3] = MD5M_D;
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
u32x ipad[4];
u32x opad[4];
Initial commit
2015-12-04 15:47:52 +01:00
hmac_md5_pad (w0_t, w1_t, w2_t, w3_t, ipad, opad);
int left;
int off;
for (left = userdomain_len, off = 0; left >= 56; left -= 64, off += 16)
{
w0_t[0] = s_userdomain_buf[off + 0];
w0_t[1] = s_userdomain_buf[off + 1];
w0_t[2] = s_userdomain_buf[off + 2];
w0_t[3] = s_userdomain_buf[off + 3];
w1_t[0] = s_userdomain_buf[off + 4];
w1_t[1] = s_userdomain_buf[off + 5];
w1_t[2] = s_userdomain_buf[off + 6];
w1_t[3] = s_userdomain_buf[off + 7];
w2_t[0] = s_userdomain_buf[off + 8];
w2_t[1] = s_userdomain_buf[off + 9];
w2_t[2] = s_userdomain_buf[off + 10];
w2_t[3] = s_userdomain_buf[off + 11];
w3_t[0] = s_userdomain_buf[off + 12];
w3_t[1] = s_userdomain_buf[off + 13];
w3_t[2] = s_userdomain_buf[off + 14];
w3_t[3] = s_userdomain_buf[off + 15];
md5_transform (w0_t, w1_t, w2_t, w3_t, ipad);
}
w0_t[0] = s_userdomain_buf[off + 0];
w0_t[1] = s_userdomain_buf[off + 1];
w0_t[2] = s_userdomain_buf[off + 2];
w0_t[3] = s_userdomain_buf[off + 3];
w1_t[0] = s_userdomain_buf[off + 4];
w1_t[1] = s_userdomain_buf[off + 5];
w1_t[2] = s_userdomain_buf[off + 6];
w1_t[3] = s_userdomain_buf[off + 7];
w2_t[0] = s_userdomain_buf[off + 8];
w2_t[1] = s_userdomain_buf[off + 9];
w2_t[2] = s_userdomain_buf[off + 10];
w2_t[3] = s_userdomain_buf[off + 11];
w3_t[0] = s_userdomain_buf[off + 12];
w3_t[1] = s_userdomain_buf[off + 13];
w3_t[2] = (64 + userdomain_len) * 8;
w3_t[3] = 0;
hmac_md5_run (w0_t, w1_t, w2_t, w3_t, ipad, opad, digest);
w0_t[0] = digest[0];
w0_t[1] = digest[1];
w0_t[2] = digest[2];
w0_t[3] = digest[3];
w1_t[0] = 0;
w1_t[1] = 0;
w1_t[2] = 0;
w1_t[3] = 0;
w2_t[0] = 0;
w2_t[1] = 0;
w2_t[2] = 0;
w2_t[3] = 0;
w3_t[0] = 0;
w3_t[1] = 0;
w3_t[2] = 0;
w3_t[3] = 0;
digest[0] = MD5M_A;
digest[1] = MD5M_B;
digest[2] = MD5M_C;
digest[3] = MD5M_D;
hmac_md5_pad (w0_t, w1_t, w2_t, w3_t, ipad, opad);
for (left = chall_len, off = 0; left >= 56; left -= 64, off += 16)
{
w0_t[0] = s_chall_buf[off + 0];
w0_t[1] = s_chall_buf[off + 1];
w0_t[2] = s_chall_buf[off + 2];
w0_t[3] = s_chall_buf[off + 3];
w1_t[0] = s_chall_buf[off + 4];
w1_t[1] = s_chall_buf[off + 5];
w1_t[2] = s_chall_buf[off + 6];
w1_t[3] = s_chall_buf[off + 7];
w2_t[0] = s_chall_buf[off + 8];
w2_t[1] = s_chall_buf[off + 9];
w2_t[2] = s_chall_buf[off + 10];
w2_t[3] = s_chall_buf[off + 11];
w3_t[0] = s_chall_buf[off + 12];
w3_t[1] = s_chall_buf[off + 13];
w3_t[2] = s_chall_buf[off + 14];
w3_t[3] = s_chall_buf[off + 15];
md5_transform (w0_t, w1_t, w2_t, w3_t, ipad);
}
w0_t[0] = s_chall_buf[off + 0];
w0_t[1] = s_chall_buf[off + 1];
w0_t[2] = s_chall_buf[off + 2];
w0_t[3] = s_chall_buf[off + 3];
w1_t[0] = s_chall_buf[off + 4];
w1_t[1] = s_chall_buf[off + 5];
w1_t[2] = s_chall_buf[off + 6];
w1_t[3] = s_chall_buf[off + 7];
w2_t[0] = s_chall_buf[off + 8];
w2_t[1] = s_chall_buf[off + 9];
w2_t[2] = s_chall_buf[off + 10];
w2_t[3] = s_chall_buf[off + 11];
w3_t[0] = s_chall_buf[off + 12];
w3_t[1] = s_chall_buf[off + 13];
w3_t[2] = (64 + chall_len) * 8;
w3_t[3] = 0;
hmac_md5_run (w0_t, w1_t, w2_t, w3_t, ipad, opad, digest);
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
COMPARE_M_SIMD (digest[0], digest[3], digest[2], digest[1]);
Initial commit
2015-12-04 15:47:52 +01:00
}
}
- Added inline declaration to functions from simd.c, common.c, rp.c and types_ocl.c to increase performance - Dropped static declaration from functions in all kernel to achieve OpenCL 1.1 compatibility - Added -cl-std=CL1.1 to all kernel build options - Created environment variable to inform NVidia OpenCL runtime to not create its own kernel cache - Created environment variable to inform pocl OpenCL runtime to not create its own kernel cache
2016-05-01 23:15:26 +02:00
void m05600s (u32 w0[4], u32 w1[4], u32 w2[4], u32 w3[4], const u32 pw_len, __global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global netntlm_t *netntlm_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, __local u32 *s_userdomain_buf, __local u32 *s_chall_buf)
Initial commit
2015-12-04 15:47:52 +01:00
{
/**
* modifier
*/
const u32 gid = get_global_id (0);
const u32 lid = get_local_id (0);
Cleanup -m 56xx kernels to latest standard
2016-04-12 21:21:35 +02:00
/**
* prepare
*/
const u32 userdomain_len = netntlm_bufs[salt_pos].user_len
+ netntlm_bufs[salt_pos].domain_len;
const u32 chall_len = netntlm_bufs[salt_pos].srvchall_len
+ netntlm_bufs[salt_pos].clichall_len;
Initial commit
2015-12-04 15:47:52 +01:00
/**
* digest
*/
const u32 search[4] =
{
digests_buf[digests_offset].digest_buf[DGST_R0],
digests_buf[digests_offset].digest_buf[DGST_R1],
digests_buf[digests_offset].digest_buf[DGST_R2],
digests_buf[digests_offset].digest_buf[DGST_R3]
};
/**
* loop
*/
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w0l = w0[0];
Initial commit
2015-12-04 15:47:52 +01:00
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
for (u32 il_pos = 0; il_pos < il_cnt; il_pos += VECT_SIZE)
Initial commit
2015-12-04 15:47:52 +01:00
{
Prepare NEW_SIMD_MODE for -a 1 kernels
2016-02-20 16:13:06 +01:00
const u32x w0r = ix_create_bft (bfs_buf, il_pos);
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
const u32x w0lr = w0l | w0r;
Cleanup -m 56xx kernels to latest standard
2016-04-12 21:21:35 +02:00
/**
* pads
*/
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
u32x w0_t[4];
u32x w1_t[4];
u32x w2_t[4];
u32x w3_t[4];
w0_t[0] = w0lr;
w0_t[1] = w0[1];
w0_t[2] = w0[2];
w0_t[3] = w0[3];
w1_t[0] = w1[0];
w1_t[1] = w1[1];
w1_t[2] = w1[2];
w1_t[3] = w1[3];
w2_t[0] = w2[0];
w2_t[1] = w2[1];
w2_t[2] = w2[2];
w2_t[3] = w2[3];
w3_t[0] = w3[0];
w3_t[1] = w3[1];
w3_t[2] = w3[2];
w3_t[3] = w3[3];
u32x digest[4];
Initial commit
2015-12-04 15:47:52 +01:00
digest[0] = MD4M_A;
digest[1] = MD4M_B;
digest[2] = MD4M_C;
digest[3] = MD4M_D;
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
md4_transform (w0_t, w1_t, w2_t, w3_t, digest);
Initial commit
2015-12-04 15:47:52 +01:00
w0_t[0] = digest[0];
w0_t[1] = digest[1];
w0_t[2] = digest[2];
w0_t[3] = digest[3];
w1_t[0] = 0;
w1_t[1] = 0;
w1_t[2] = 0;
w1_t[3] = 0;
w2_t[0] = 0;
w2_t[1] = 0;
w2_t[2] = 0;
w2_t[3] = 0;
w3_t[0] = 0;
w3_t[1] = 0;
w3_t[2] = 0;
w3_t[3] = 0;
digest[0] = MD5M_A;
digest[1] = MD5M_B;
digest[2] = MD5M_C;
digest[3] = MD5M_D;
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
u32x ipad[4];
u32x opad[4];
Initial commit
2015-12-04 15:47:52 +01:00
hmac_md5_pad (w0_t, w1_t, w2_t, w3_t, ipad, opad);
int left;
int off;
for (left = userdomain_len, off = 0; left >= 56; left -= 64, off += 16)
{
w0_t[0] = s_userdomain_buf[off + 0];
w0_t[1] = s_userdomain_buf[off + 1];
w0_t[2] = s_userdomain_buf[off + 2];
w0_t[3] = s_userdomain_buf[off + 3];
w1_t[0] = s_userdomain_buf[off + 4];
w1_t[1] = s_userdomain_buf[off + 5];
w1_t[2] = s_userdomain_buf[off + 6];
w1_t[3] = s_userdomain_buf[off + 7];
w2_t[0] = s_userdomain_buf[off + 8];
w2_t[1] = s_userdomain_buf[off + 9];
w2_t[2] = s_userdomain_buf[off + 10];
w2_t[3] = s_userdomain_buf[off + 11];
w3_t[0] = s_userdomain_buf[off + 12];
w3_t[1] = s_userdomain_buf[off + 13];
w3_t[2] = s_userdomain_buf[off + 14];
w3_t[3] = s_userdomain_buf[off + 15];
md5_transform (w0_t, w1_t, w2_t, w3_t, ipad);
}
w0_t[0] = s_userdomain_buf[off + 0];
w0_t[1] = s_userdomain_buf[off + 1];
w0_t[2] = s_userdomain_buf[off + 2];
w0_t[3] = s_userdomain_buf[off + 3];
w1_t[0] = s_userdomain_buf[off + 4];
w1_t[1] = s_userdomain_buf[off + 5];
w1_t[2] = s_userdomain_buf[off + 6];
w1_t[3] = s_userdomain_buf[off + 7];
w2_t[0] = s_userdomain_buf[off + 8];
w2_t[1] = s_userdomain_buf[off + 9];
w2_t[2] = s_userdomain_buf[off + 10];
w2_t[3] = s_userdomain_buf[off + 11];
w3_t[0] = s_userdomain_buf[off + 12];
w3_t[1] = s_userdomain_buf[off + 13];
w3_t[2] = (64 + userdomain_len) * 8;
w3_t[3] = 0;
hmac_md5_run (w0_t, w1_t, w2_t, w3_t, ipad, opad, digest);
w0_t[0] = digest[0];
w0_t[1] = digest[1];
w0_t[2] = digest[2];
w0_t[3] = digest[3];
w1_t[0] = 0;
w1_t[1] = 0;
w1_t[2] = 0;
w1_t[3] = 0;
w2_t[0] = 0;
w2_t[1] = 0;
w2_t[2] = 0;
w2_t[3] = 0;
w3_t[0] = 0;
w3_t[1] = 0;
w3_t[2] = 0;
w3_t[3] = 0;
digest[0] = MD5M_A;
digest[1] = MD5M_B;
digest[2] = MD5M_C;
digest[3] = MD5M_D;
hmac_md5_pad (w0_t, w1_t, w2_t, w3_t, ipad, opad);
for (left = chall_len, off = 0; left >= 56; left -= 64, off += 16)
{
w0_t[0] = s_chall_buf[off + 0];
w0_t[1] = s_chall_buf[off + 1];
w0_t[2] = s_chall_buf[off + 2];
w0_t[3] = s_chall_buf[off + 3];
w1_t[0] = s_chall_buf[off + 4];
w1_t[1] = s_chall_buf[off + 5];
w1_t[2] = s_chall_buf[off + 6];
w1_t[3] = s_chall_buf[off + 7];
w2_t[0] = s_chall_buf[off + 8];
w2_t[1] = s_chall_buf[off + 9];
w2_t[2] = s_chall_buf[off + 10];
w2_t[3] = s_chall_buf[off + 11];
w3_t[0] = s_chall_buf[off + 12];
w3_t[1] = s_chall_buf[off + 13];
w3_t[2] = s_chall_buf[off + 14];
w3_t[3] = s_chall_buf[off + 15];
md5_transform (w0_t, w1_t, w2_t, w3_t, ipad);
}
w0_t[0] = s_chall_buf[off + 0];
w0_t[1] = s_chall_buf[off + 1];
w0_t[2] = s_chall_buf[off + 2];
w0_t[3] = s_chall_buf[off + 3];
w1_t[0] = s_chall_buf[off + 4];
w1_t[1] = s_chall_buf[off + 5];
w1_t[2] = s_chall_buf[off + 6];
w1_t[3] = s_chall_buf[off + 7];
w2_t[0] = s_chall_buf[off + 8];
w2_t[1] = s_chall_buf[off + 9];
w2_t[2] = s_chall_buf[off + 10];
w2_t[3] = s_chall_buf[off + 11];
w3_t[0] = s_chall_buf[off + 12];
w3_t[1] = s_chall_buf[off + 13];
w3_t[2] = (64 + chall_len) * 8;
w3_t[3] = 0;
hmac_md5_run (w0_t, w1_t, w2_t, w3_t, ipad, opad, digest);
Converted _a3 kernels, use SIMD for CPU and GPU
2016-01-23 15:32:31 +01:00
COMPARE_S_SIMD (digest[0], digest[3], digest[2], digest[1]);
Initial commit
2015-12-04 15:47:52 +01:00
}
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
__kernel void m05600_m04 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global netntlm_t *netntlm_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 15:47:52 +01:00
{
/**
* modifier
*/
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
const u32 gid = get_global_id (0);
Initial commit
2015-12-04 15:47:52 +01:00
const u32 lid = get_local_id (0);
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
const u32 lsz = get_local_size (0);
Initial commit
2015-12-04 15:47:52 +01:00
/**
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
* salt
Initial commit
2015-12-04 15:47:52 +01:00
*/
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
__local u32 s_userdomain_buf[64];
for (u32 i = lid; i < 64; i += lsz)
{
s_userdomain_buf[i] = netntlm_bufs[salt_pos].userdomain_buf[i];
}
__local u32 s_chall_buf[256];
for (u32 i = lid; i < 256; i += lsz)
{
s_chall_buf[i] = netntlm_bufs[salt_pos].chall_buf[i];
}
barrier (CLK_LOCAL_MEM_FENCE);
if (gid >= gid_max) return;
const u32 userdomain_len = netntlm_bufs[salt_pos].user_len
+ netntlm_bufs[salt_pos].domain_len;
const u32 chall_len = netntlm_bufs[salt_pos].srvchall_len
+ netntlm_bufs[salt_pos].clichall_len;
/**
* base
*/
Initial commit
2015-12-04 15:47:52 +01:00
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w0[4];
Initial commit
2015-12-04 15:47:52 +01:00
w0[0] = pws[gid].i[ 0];
w0[1] = pws[gid].i[ 1];
w0[2] = pws[gid].i[ 2];
w0[3] = pws[gid].i[ 3];
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w1[4];
Initial commit
2015-12-04 15:47:52 +01:00
w1[0] = 0;
w1[1] = 0;
w1[2] = 0;
w1[3] = 0;
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w2[4];
Initial commit
2015-12-04 15:47:52 +01:00
w2[0] = 0;
w2[1] = 0;
w2[2] = 0;
w2[3] = 0;
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w3[4];
Initial commit
2015-12-04 15:47:52 +01:00
w3[0] = 0;
w3[1] = 0;
w3[2] = pws[gid].i[14];
w3[3] = 0;
const u32 pw_len = pws[gid].pw_len;
/**
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
m05600m (w0, w1, w2, w3, pw_len, pws, rules_buf, combs_buf, bfs_buf, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, netntlm_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset, s_userdomain_buf, s_chall_buf);
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
__kernel void m05600_m08 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global netntlm_t *netntlm_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
{
/**
* modifier
*/
const u32 gid = get_global_id (0);
const u32 lid = get_local_id (0);
const u32 lsz = get_local_size (0);
/**
* salt
Initial commit
2015-12-04 15:47:52 +01:00
*/
__local u32 s_userdomain_buf[64];
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
for (u32 i = lid; i < 64; i += lsz)
Initial commit
2015-12-04 15:47:52 +01:00
{
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
s_userdomain_buf[i] = netntlm_bufs[salt_pos].userdomain_buf[i];
Initial commit
2015-12-04 15:47:52 +01:00
}
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
__local u32 s_chall_buf[256];
Initial commit
2015-12-04 15:47:52 +01:00
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
for (u32 i = lid; i < 256; i += lsz)
{
s_chall_buf[i] = netntlm_bufs[salt_pos].chall_buf[i];
}
Initial commit
2015-12-04 15:47:52 +01:00
barrier (CLK_LOCAL_MEM_FENCE);
if (gid >= gid_max) return;
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
const u32 userdomain_len = netntlm_bufs[salt_pos].user_len
+ netntlm_bufs[salt_pos].domain_len;
Initial commit
2015-12-04 15:47:52 +01:00
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
const u32 chall_len = netntlm_bufs[salt_pos].srvchall_len
+ netntlm_bufs[salt_pos].clichall_len;
Initial commit
2015-12-04 15:47:52 +01:00
/**
* base
*/
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w0[4];
Initial commit
2015-12-04 15:47:52 +01:00
w0[0] = pws[gid].i[ 0];
w0[1] = pws[gid].i[ 1];
w0[2] = pws[gid].i[ 2];
w0[3] = pws[gid].i[ 3];
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w1[4];
Initial commit
2015-12-04 15:47:52 +01:00
w1[0] = pws[gid].i[ 4];
w1[1] = pws[gid].i[ 5];
w1[2] = pws[gid].i[ 6];
w1[3] = pws[gid].i[ 7];
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w2[4];
Initial commit
2015-12-04 15:47:52 +01:00
w2[0] = 0;
w2[1] = 0;
w2[2] = 0;
w2[3] = 0;
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w3[4];
Initial commit
2015-12-04 15:47:52 +01:00
w3[0] = 0;
w3[1] = 0;
w3[2] = pws[gid].i[14];
w3[3] = 0;
const u32 pw_len = pws[gid].pw_len;
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
m05600m (w0, w1, w2, w3, pw_len, pws, rules_buf, combs_buf, bfs_buf, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, netntlm_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset, s_userdomain_buf, s_chall_buf);
Initial commit
2015-12-04 15:47:52 +01:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
__kernel void m05600_m16 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global netntlm_t *netntlm_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 15:47:52 +01:00
{
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
__kernel void m05600_s04 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global netntlm_t *netntlm_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 15:47:52 +01:00
{
/**
* modifier
*/
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
const u32 gid = get_global_id (0);
Initial commit
2015-12-04 15:47:52 +01:00
const u32 lid = get_local_id (0);
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
const u32 lsz = get_local_size (0);
Initial commit
2015-12-04 15:47:52 +01:00
/**
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
* salt
Initial commit
2015-12-04 15:47:52 +01:00
*/
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
__local u32 s_userdomain_buf[64];
for (u32 i = lid; i < 64; i += lsz)
{
s_userdomain_buf[i] = netntlm_bufs[salt_pos].userdomain_buf[i];
}
__local u32 s_chall_buf[256];
for (u32 i = lid; i < 256; i += lsz)
{
s_chall_buf[i] = netntlm_bufs[salt_pos].chall_buf[i];
}
barrier (CLK_LOCAL_MEM_FENCE);
if (gid >= gid_max) return;
const u32 userdomain_len = netntlm_bufs[salt_pos].user_len
+ netntlm_bufs[salt_pos].domain_len;
const u32 chall_len = netntlm_bufs[salt_pos].srvchall_len
+ netntlm_bufs[salt_pos].clichall_len;
/**
* base
*/
Initial commit
2015-12-04 15:47:52 +01:00
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w0[4];
Initial commit
2015-12-04 15:47:52 +01:00
w0[0] = pws[gid].i[ 0];
w0[1] = pws[gid].i[ 1];
w0[2] = pws[gid].i[ 2];
w0[3] = pws[gid].i[ 3];
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w1[4];
Initial commit
2015-12-04 15:47:52 +01:00
w1[0] = 0;
w1[1] = 0;
w1[2] = 0;
w1[3] = 0;
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w2[4];
Initial commit
2015-12-04 15:47:52 +01:00
w2[0] = 0;
w2[1] = 0;
w2[2] = 0;
w2[3] = 0;
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w3[4];
Initial commit
2015-12-04 15:47:52 +01:00
w3[0] = 0;
w3[1] = 0;
w3[2] = pws[gid].i[14];
w3[3] = 0;
const u32 pw_len = pws[gid].pw_len;
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
m05600s (w0, w1, w2, w3, pw_len, pws, rules_buf, combs_buf, bfs_buf, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, netntlm_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset, s_userdomain_buf, s_chall_buf);
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
__kernel void m05600_s08 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global netntlm_t *netntlm_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
{
/**
* modifier
*/
const u32 gid = get_global_id (0);
const u32 lid = get_local_id (0);
const u32 lsz = get_local_size (0);
Initial commit
2015-12-04 15:47:52 +01:00
/**
* salt
*/
__local u32 s_userdomain_buf[64];
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
for (u32 i = lid; i < 64; i += lsz)
Initial commit
2015-12-04 15:47:52 +01:00
{
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
s_userdomain_buf[i] = netntlm_bufs[salt_pos].userdomain_buf[i];
Initial commit
2015-12-04 15:47:52 +01:00
}
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
__local u32 s_chall_buf[256];
Initial commit
2015-12-04 15:47:52 +01:00
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
for (u32 i = lid; i < 256; i += lsz)
{
s_chall_buf[i] = netntlm_bufs[salt_pos].chall_buf[i];
}
Initial commit
2015-12-04 15:47:52 +01:00
barrier (CLK_LOCAL_MEM_FENCE);
if (gid >= gid_max) return;
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
const u32 userdomain_len = netntlm_bufs[salt_pos].user_len
+ netntlm_bufs[salt_pos].domain_len;
Initial commit
2015-12-04 15:47:52 +01:00
Upgrade kernel to support dynamic local work sizes
2016-01-19 16:06:03 +01:00
const u32 chall_len = netntlm_bufs[salt_pos].srvchall_len
+ netntlm_bufs[salt_pos].clichall_len;
Initial commit
2015-12-04 15:47:52 +01:00
/**
* base
*/
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w0[4];
Initial commit
2015-12-04 15:47:52 +01:00
w0[0] = pws[gid].i[ 0];
w0[1] = pws[gid].i[ 1];
w0[2] = pws[gid].i[ 2];
w0[3] = pws[gid].i[ 3];
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w1[4];
Initial commit
2015-12-04 15:47:52 +01:00
w1[0] = pws[gid].i[ 4];
w1[1] = pws[gid].i[ 5];
w1[2] = pws[gid].i[ 6];
w1[3] = pws[gid].i[ 7];
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w2[4];
Initial commit
2015-12-04 15:47:52 +01:00
w2[0] = 0;
w2[1] = 0;
w2[2] = 0;
w2[3] = 0;
- Dropped all vector code since new GPU's are all scalar, makes the code much easier - Some performance on low-end GPU may drop because of that, but only for a few hash-modes - Dropped scalar code (aka warp) since we do not have any vector datatypes anymore - Renamed C++ overloading functions memcat32_9 -> memcat_c32_w4x4_a3x4 - Still need to fix kernels to new function names, needs to be done manually - Temperature Management needs to be rewritten partially because of conflicting datatypes names - Added code to create different codepaths for NV on AMD in runtime in host (see data.vendor_id) - Added code to create different codepaths for NV on AMD in runtime in kernels (see IS_NV and IS_AMD) - First tests working for -m 0, for example - Great performance increases in general for NV so far - Tested amp_* and markov_* kernel - Migrated special NV optimizations for rule processor
2015-12-15 12:04:22 +01:00
u32 w3[4];
Initial commit
2015-12-04 15:47:52 +01:00
w3[0] = 0;
w3[1] = 0;
w3[2] = pws[gid].i[14];
w3[3] = 0;
const u32 pw_len = pws[gid].pw_len;
/**
* main
*/
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
m05600s (w0, w1, w2, w3, pw_len, pws, rules_buf, combs_buf, bfs_buf, tmps, hooks, bitmaps_buf_s1_a, bitmaps_buf_s1_b, bitmaps_buf_s1_c, bitmaps_buf_s1_d, bitmaps_buf_s2_a, bitmaps_buf_s2_b, bitmaps_buf_s2_c, bitmaps_buf_s2_d, plains_buf, digests_buf, hashes_shown, salt_bufs, netntlm_bufs, d_return_buf, d_scryptV_buf, bitmap_mask, bitmap_shift1, bitmap_shift2, salt_pos, loop_pos, loop_cnt, il_cnt, digests_cnt, digests_offset, s_userdomain_buf, s_chall_buf);
Initial commit
2015-12-04 15:47:52 +01:00
}
Fixed two major problems 1) SIMD code for all attack-mode Macro vector_accessible() was not refactored and missing completely. Had to rename variables rules_cnt, combs_cnt and bfs_cnt into il_cnt which was a good thing anyway as with new SIMD code they all act in the same way. 2) SIMD code for attack-mode 0 With new SIMD code, apply_rules_vect() has to return u32 not u32x. This has massive impact on all *_a0 kernels. I've rewritten most of them. Deep testing using test.sh is still required. Some kernel need more fixes: - Some are kind of completely incompatible like m10400 but they still use old check_* includes, we should get rid of them as they are no longer neccessary as we have simd.c - Some have a chance but require additional effort like m11500. We can use commented out "#define NEW_SIMD_CODE" to find them This change can have negative impact on -a0 performance for device that require vectorization. That is mostly CPU devices. New GPU's are all scalar, so they wont get hurt by this. This change also proofes that there's no way to efficiently vectorize kernel rules with new SIMD code, but it enables the addition of the rule functions like @ that we were missing for some long time. This is a TODO.
2016-02-27 17:18:54 +01:00
__kernel void m05600_s16 (__global pw_t *pws, __global kernel_rule_t *rules_buf, __global comb_t *combs_buf, __global bf_t *bfs_buf, __global void *tmps, __global void *hooks, __global u32 *bitmaps_buf_s1_a, __global u32 *bitmaps_buf_s1_b, __global u32 *bitmaps_buf_s1_c, __global u32 *bitmaps_buf_s1_d, __global u32 *bitmaps_buf_s2_a, __global u32 *bitmaps_buf_s2_b, __global u32 *bitmaps_buf_s2_c, __global u32 *bitmaps_buf_s2_d, __global plain_t *plains_buf, __global digest_t *digests_buf, __global u32 *hashes_shown, __global salt_t *salt_bufs, __global netntlm_t *netntlm_bufs, __global u32 *d_return_buf, __global u32 *d_scryptV_buf, const u32 bitmap_mask, const u32 bitmap_shift1, const u32 bitmap_shift2, const u32 salt_pos, const u32 loop_pos, const u32 loop_cnt, const u32 il_cnt, const u32 digests_cnt, const u32 digests_offset, const u32 combs_mode, const u32 gid_max)
Initial commit
2015-12-04 15:47:52 +01:00
{
}
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